[Vivado] Revert Vivado path changes

- Paths with spaces are not supported. Period.
XedaHQ · Oct 27, 2024 · f44937c · f44937c
1 parent 6c87cba
commit f44937c
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Showing 2 changed files with 9 additions and 13 deletions.
diff --git a/src/xeda/flows/vivado/templates/vivado_sim.tcl b/src/xeda/flows/vivado/templates/vivado_sim.tcl
@@ -19,17 +19,17 @@ puts "\n===========================( Analyzing HDL Sources )====================
 {%- for src in design.sim_sources %}
 {%- if src.type.name == "Verilog" %}
 puts "Analyzing Verilog file {{src.file}}"
-if { [catch {eval exec xvlog ${analyze_flags} {"{{src.file}}"}} error]} {
+if { [catch {eval exec xvlog ${analyze_flags} "{{src.file}}"} error]} {
     errorExit $error
 }
 {%- elif src.type.name == "SystemVerilog" %}
 puts "Analyzing SystemVerilog file {{src.file}}"
-if { [catch {eval exec xvlog ${analyze_flags} -sv {"{{src.file}}"}} error]} {
+if { [catch {eval exec xvlog ${analyze_flags} -sv "{{src.file}}"} error]} {
     errorExit $error
 }
 {%- elif src.type.name == "Vhdl" %}
 puts "Analyzing VHDL file {{src.file}} {% if design.language.vhdl.standard -%} \[VHDL {{design.language.vhdl.standard}}\] {%- endif %}"
-if { [catch {eval exec xvhdl ${analyze_flags} {% if design.language.vhdl.standard in ("08", "2008") %} -2008 {% elif design.language.vhdl.standard in ("93", "1993") %} -93_mode {% endif %} {"{{src.file}}"}} error]} {
+if { [catch {eval exec xvhdl ${analyze_flags} {% if design.language.vhdl.standard in ("08", "2008") %} -2008 {% elif design.language.vhdl.standard in ("93", "1993") %} -93_mode {% endif %} "{{src.file}}"} error]} {
     errorExit $error
 }
 {%- endif %}

diff --git a/src/xeda/flows/vivado/templates/vivado_synth.tcl b/src/xeda/flows/vivado/templates/vivado_synth.tcl
@@ -14,17 +14,17 @@ puts "\n=====================( Read Design Files and Constraints )==============
 {%- for src in design.rtl.sources %}
 {%- if src.type.name == "Verilog" %}
 puts "Reading Verilog file {{src.file}}"
-if { [catch {read_verilog {"{{src.file}}"}} myError]} {
+if { [catch {read_verilog "{{src.file}}"} myError]} {
   errorExit $myError
 }
 {%- elif src.type.name == "SystemVerilog" %}
 puts "Reading SystemVerilog file {{src.file}}"
-if { [catch {read_verilog -sv {"{{src.file}}"}} myError]} {
+if { [catch {read_verilog -sv "{{src.file}}"} myError]} {
   errorExit $myError
 }
 {%- elif src.type.name == "Vhdl" %}
 puts "Reading VHDL file {{src.file}}"
-if { [catch {read_vhdl {% if design.language.vhdl.standard in ("08", "2008") -%} -vhdl2008 {% endif -%} {"{{src.file}}"}} myError]} {
+if { [catch {read_vhdl {% if design.language.vhdl.standard in ("08", "2008") -%} -vhdl2008 {% endif -%} "{{src.file}}"} myError]} {
   errorExit $myError
 }
 {%- endif %}
@@ -86,13 +86,9 @@ set reports_tcl_path [file normalize {{reports_tcl}}]
 
 add_files -fileset utils_1 -norecurse {{reports_tcl}}
 
-puts 1
-set_property STEPS.OPT_DESIGN.TCL.POST {$reports_tcl_path} [get_runs impl_1]
-puts 2
-set_property STEPS.PLACE_DESIGN.TCL.POST {$reports_tcl_path} [get_runs impl_1]
-puts 3
-set_property STEPS.ROUTE_DESIGN.TCL.POST {$reports_tcl_path} [get_runs impl_1]
-puts 3
+set_property STEPS.OPT_DESIGN.TCL.POST $reports_tcl_path [get_runs impl_1]
+set_property STEPS.PLACE_DESIGN.TCL.POST $reports_tcl_path [get_runs impl_1]
+set_property STEPS.ROUTE_DESIGN.TCL.POST $reports_tcl_path [get_runs impl_1]
 
 puts "\n=============================( Running Synthesis )============================="
 reset_run synth_1