Bump to llvm upstream (2024-01-01) #128
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…n X86InstrArithmetic.td This patch is to extract the NFC in llvm#76319 into a separate commit.
The current command will raise an error: > The `opt -passname` syntax for the new pass manager is not supported, please use `opt -passes=<pipeline>` (or the `-p` alias for a more concise version). Update the usage now.
Similar to the existing isZExtFree(SDValue, EVT) wrapper, this will allow targets to override for specific cases (e.g. free truncation of an ext/extload node). But for now its just used to wrap the existing isTruncateFree(EVT, EVT) call.
Previously the JITLink MachO backends (aarch64 and x86-64) only looked at the fixup block to determine which symbol was being fixed up. This assumption breaks if both symbols used in the subtractor are in the same block. The fix is to check for such cases and use the offsets of each symbol to decide which is being fixed up. The issue only resulted in incorrect behavior for negative-delta relocations, so the testcases use eh-frames with explicit edges for the CIE-pointer field in FDEs (since these are negative-deltas). rdar://119351329
This is a follow up to llvm#75635 which broke the build on Fuchsia. We don't support ifunc on Fuchsia so we shouldn't define __init_cpu_features. For __init_cpu_features_resolver we have to use _zx_system_get_features as a Zircon native solution.
This patch folds xor of icmps into a single comparison using range-based reasoning as `foldAndOrOfICmpsUsingRanges` does. Fixes llvm#70928.
…6275) Most basic block do not need to query dominates. Defer initialization of InstrPosIndexes to first query for each MBB.
…intrinsics. NFC. (llvm#76317) Zvfbfmin doesn't need Zfbfmin also enabled.
…ateDecl (llvm#74919) Skip checking `TemplateTypeParmDecl ` in `VisitTypeAliasTemplateDecl`. [Fix this crash](llvm#74765) Co-authored-by: huqizhi <836744285@qq.com>
llvm#76158) This patch also add tests whose masks are too narrow to combine. I think it can help us to find out bugs caused by too large known bits.
…lvm#76349) This test file mainly asserts the implementation details of libc++, so it should be in the `libcxx` subdirectory.
R_LARCH_CALL36 was designed for function call on medium code model where
the 2 instructions (pcaddu18i + jirl) must be adjacent. This is expected
to replace current medium code model implementation, i.e.
R_LARCH_PCALA_{HI20,LO12} on pcalau12i + jirl.
See loongson/la-abi-specs#3 for more details.
Otherwise link may fail if user provided additional library to link with via CMAKE_EXE_LINKER_FLAGS. Concrete example is using custom allocator, LLVMSupport provides needed -lpthread in that case. Closes: llvm#65424
…ary (llvm#66598) Currently there's no component for LLVMPolly and PollyISL, however they are added to exports whether or not they are installed. This commit calls add_llvm_install_targets in the add_polly_library function to allow installation of LLVMPolly and PollyISL via distribution components, so they can be installed without also installing libPolly.a. Closes: llvm#66598
Several buildbots report: ld.lld: error: failed to open /dev/null: Cannot allocate memory For example: - https://lab.llvm.org/buildbot/#/builders/184/builds/8842 - https://lab.llvm.org/buildbot/#/builders/247/builds/12559
Update DAG ISel to support 64bit versions S_FF1_I32_B64 and S_FLBIT_I32_B664 --------- Co-authored-by: Acim Maravic <Acim.Maravic@amd.com>
…#76101) Introduce a new (off by default) clang tidy check to ensure that variables of a specific type are always used even if -Wunused-variables wouldn't generate a warning. This check has already caught a couple of different bugs on the codebase I work on, where not handling a future means that lifetimes may not be kept alive properly as an async chunk of code may run after a class has been destroyed, etc. I would like to upstream it because I believe there could be other applications of this check that would be useful in different contexts. --------- Signed-off-by: Tyler Rockwood <rockwood@redpanda.com>
…-non-trivial-variable Added -fexceptions switch to test. It were missing in llvm#76101.
The check makes sure that the result for getZExtValue is guaranteed to fit into 64 bit.
… canonicalization (llvm#76583) llvm@7d7001b canonicalizes `(gep i8, X, (ptrtoint Y) - (ptrtoint X))` into `bitcast Y` iff `X` and `Y` have the same underlying object. I find that the result of this pattern is usually used as an operand of an icmp in some real-world applications. I think we can do the canonicalization if the result is only used by icmps/ptrtoints. Alive2: https://alive2.llvm.org/ce/z/j4-HJZ
Remove the llvm_unreachable from getSolarisLibSuffix(). The code path is reachable. In the case of an unsupported architecture we're not worrying about trying to actually find the library paths, and I don't think it makes sense for the Driver to crash. Fixes llvm#58334
Added to allow generating these intrinsics in out-of-tree MLIR passes. Co-authored-by: Yoni Lavi <yoni.lavi@nextsilicon.com>
Use `UTC_ARGS: --version 4`.
Fix this issue llvm#72843 . For naked function, assembly might be using an argument, or otherwise rely on the frame layout, so don't transformConstExprCastCall
These come from the legalization of other operations, but it makes sense to split the operations into legal sizes before lowering them.
As ImmVal is unsigned, it will always be >= 0
) The transform.structured.eliminate_empty_tensors can produce mis-typed IR when traversing use-def chains past tensor reshaping operations for sharing candidates. This results in Linalg operations whose output types do not match their 'outs' arguments. This patch filters out candidate tensor.empty operations when their types do not match the candidate input operand.
You can test this locally with the following command:darker --check --diff -r 7ed5dd2c28e5035f556480fd6d56d240a45bd93c...713be044c72cd463d9aad7084815ab018fa074cc lldb/test/API/python_api/sbvalue_synthetic/TestSBValueSynthetic.py lldb/test/API/python_api/sbvalue_synthetic/formatter.py libcxx/utils/generate_feature_test_macro_components.py lldb/test/API/lang/cpp/unique-types4/TestUniqueTypes4.py llvm/utils/git/code-format-helper.py mlir/test/python/pass_manager.pyView the diff from darker here.--- lldb/test/API/lang/cpp/unique-types4/TestUniqueTypes4.py 2023-12-19 14:25:23.000000 +0000
+++ lldb/test/API/lang/cpp/unique-types4/TestUniqueTypes4.py 2024-03-08 15:49:43.817684 +0000
@@ -29,16 +29,16 @@
"expression ns::Bar<int>::value", substrs=["'Bar' in namespace 'ns'"], error=True
)
self.expect_expr("ns::FooDouble::value", result_type="double", result_value="0")
self.expect_expr("ns::FooInt::value", result_type="int", result_value="0")
- @skipIfWindows # https://github.com/llvm/llvm-project/issues/75936
+ @skipIfWindows # https://github.com/llvm/llvm-project/issues/75936
@skipIf(compiler=no_match("clang"))
@skipIf(compiler_version=["<", "15.0"])
def test_simple_template_names(self):
self.do_test(dict(CFLAGS_EXTRAS="-gsimple-template-names"))
- @skipIfWindows # https://github.com/llvm/llvm-project/issues/75936
+ @skipIfWindows # https://github.com/llvm/llvm-project/issues/75936
@skipIf(compiler=no_match("clang"))
@skipIf(compiler_version=["<", "15.0"])
def test_no_simple_template_names(self):
self.do_test(dict(CFLAGS_EXTRAS="-gno-simple-template-names"))
|
….bump_282d50147628
commit 6b65d79 Author: Spenser Bauman <sbauman@mathworks.com> Date: Mon Jan 1 12:12:40 2024 -0500 [mlir][linalg] Fix for invalid IR in eliminate_empty_tensors (llvm#73513)
mgehre-amd
changed the title
….bump_282d50147628
jorickert
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Dec 13, 2024
This patch does 3 things:
1. Add support for optimizing the address mode of HVX load/store
instructions
2. Reduce the value of Add instruction immediates by replacing with the
difference from other Addi instructions that share common base:
For Example, If we have the below sequence of instructions: r1 =
add(r2,# 1024) ... r3 = add(r2,# 1152) ... r4 = add(r2,# 1280)
Where the register r2 has the same reaching definition, They get
modified to the below sequence:
r1 = add(r2,# 1024)
...
r3 = add(r1,# 128)
...
r4 = add(r1,# 256)
3. Fixes a bug pass where the addi instructions were modified based on a
predicated register definition, leading to incorrect output.
Eg:
INST-1: if (p0) r2 = add(r13,# 128)
INST-2: r1 = add(r2,# 1024)
INST-3: r3 = add(r2,# 1152)
INST-4: r5 = add(r2,# 1280)
In the above case, since r2's definition is predicated, we do not want
to modify the uses of r2 in INST-3/INST-4 with add(r1,#128/256)
4.Fixes a corner case
It looks like we never check whether the offset register is actually
live (not clobbered) at optimization site. Add the check whether it is
live at MBB entrance. The rest should have already been verified.
5. Fixes a bad codegen
For whatever reason we do transformation without checking if the value
in register actually reaches the user. This is second identical fix for
this pass.
Co-authored-by: Anirudh Sundar <quic_sanirudh@quicinc.com>
Co-authored-by: Sergei Larin <slarin@quicinc.com>
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