BIST-for-6bit-CLA

A Built in Self Test (BIST) controller is created in Verilog HDL to test a 6-bit Carry Lookahead Adder (CLA) utilising a 4-bit Signature Output Response Analyser (ORA).

What is a Carry Lookahead Adder?

A Carry Lookahead Adder (CLA) is a digital circuit used in computer arithmetic to perform fast addition of multi-bit numbers. Unlike simpler adders like the Ripple Carry Adder (RCA), which can be slow for large inputs due to the propagation delay of carry bits, a CLA reduces this delay by generating carry signals for each bit position in parallel. This parallel generation allows the carry signal for each bit position to be determined independently of the carry-in signal, resulting in faster addition. CLAs are widely used in digital design for applications requiring high-speed arithmetic operations, such as microprocessors and digital signal processors.

Structure of a BIST Controller

Fig 1: Block Diagram of a BIST Controller

Our BIST controller Works in the following two modes:

Mode 0 (Normal Mode) : In this mode, the CLA generates the output leading to Golden Signature
Mode 1 (Test Mode) : In this mode, the CLA generates the output leading to the Faulty Signature and the comparison takes place with the Golden signature.

We have taken two LFSR (type1) to generate test vectors for both the inputs of CLA (A & B - CUT), we have kept an ENL signal which enables both the type 1 LFSR’s.

The Output of the CUT(CLA) goes into SISR (LFSR type 2) which generates a 4bit signature when ENS (Enable SISR) signal is enable.

The ENC signal functions as a flag during signature generation in the Serial Input Shift Register (SISR). When processing a specific pattern, the ENC signal is initially low. Upon completion of signature generation, the ENC signal transitions to a high state. Consequently, the detection of a high ENC signal by the comparator or memory indicates that a signature has been successfully generated at the output of the SISR.

Pattern Generator (PG) and Serial Input Shift Register (SISR)

Fig 2: LFSR Type 1 for Pattern Generation

Fig 3: LFSR Type 2 used as an SISR for response compaction

Simulation Waveform

Fig 4: Simulation Waveform

In this simulation, we implement a Built-In Self-Test (BIST) architecture with two modes. In the first mode, we create 14 distinct patterns using Linear Feedback Shift Register (LFSR) and obtain corresponding golden signatures for each pattern. These golden signatures are stored in a memory array of size 4 x 14.

In the second mode, we introduce a fault in the carry-out of the Carry Look-Ahead (CLA) circuit. We then generate signatures for each pattern using the LFSR and compare them against the golden signatures to classify Integrated Circuits (ICs) as either functioning properly or faulty.