Merge pull request #25 from HirohitoHigashi/mrubyc_3_2

mruby/c ver 3.2対応、及び共通 I/O API 実装

.gitignore

@@ -64,3 +64,7 @@ dist/
 build/
 debug/
 release/
+
+# Mac
+.DS_Store
+._*

PIC32MX170F256B/model_dependent.c

@@ -0,0 +1,131 @@
+/*
+  MPU and board model related params.
+
+  PIC32MX170F256B
+
+  CPU clock 40MHz
+   internal oscillator + PLL
+  Peripheral clock 10MHz
+*/
+
+#include <xc.h>
+#include "model_dependent.h"
+
+
+// DEVCFG3
+#pragma config PMDL1WAY = ON    // Peripheral Module Disable Configuration->Allow only one reconfiguration
+#pragma config IOL1WAY = ON    // Peripheral Pin Select Configuration->Allow only one reconfiguration
+
+// DEVCFG2
+#pragma config FPLLIDIV = DIV_2    // PLL Input Divider->2x Divider
+#pragma config FPLLMUL = MUL_20    // PLL Multiplier->20x Multiplier
+#pragma config FPLLODIV = DIV_2    // System PLL Output Clock Divider->PLL Divide by 2
+
+// DEVCFG1
+#pragma config FNOSC = FRCPLL    // Oscillator Selection Bits->Fast RC Osc with PLL
+#pragma config FSOSCEN = OFF    // Secondary Oscillator Enable->Disabled
+#pragma config IESO = ON    // Internal/External Switch Over->Enabled
+#pragma config POSCMOD = OFF    // Primary Oscillator Configuration->Primary osc disabled
+#pragma config OSCIOFNC = OFF    // CLKO Output Signal Active on the OSCO Pin->Disabled
+#pragma config FPBDIV = DIV_4    // Peripheral Clock Divisor->Pb_Clk is Sys_Clk/4
+#pragma config FCKSM = CSDCMD    // Clock Switching and Monitor Selection->Clock Switch Disable, FSCM Disabled
+#pragma config WDTPS = PS1048576    // Watchdog Timer Postscaler->1:1048576
+#pragma config WINDIS = OFF    // Watchdog Timer Window Enable->Watchdog Timer is in Non-Window Mode
+#pragma config FWDTEN = OFF    // Watchdog Timer Enable->WDT Disabled (SWDTEN Bit Controls)
+#pragma config FWDTWINSZ = WINSZ_25    // Watchdog Timer Window Size->Window Size is 25%
+
+// DEVCFG0
+#pragma config DEBUG = OFF    // Background Debugger Enable->Debugger is Disabled
+#pragma config JTAGEN = OFF    // JTAG Enable->JTAG Disabled
+#pragma config ICESEL = ICS_PGx1    // ICE/ICD Comm Channel Select->Communicate on PGEC1/PGED1
+#pragma config PWP = OFF    // Program Flash Write Protect->Disable
+#pragma config BWP = OFF    // Boot Flash Write Protect bit->Protection Disabled
+#pragma config CP = OFF    // Code Protect->Protection Disabled
+
+
+
+/*! Remappable registers table.
+*/
+volatile uint32_t *TBL_RPxnR[] = { &RPA0R, &RPB0R, &RPC0R };
+
+
+
+/*! Initializes the device to the default states configured.
+*/
+void system_init()
+{
+  /*
+    Pin settings.
+
+    方針: ハード的に用途が決定しているもの以外は、
+    最も安全と思われる、全デジタル入力、内部プルダウンとしておく。
+
+    RA  15  14  13  12  | 11  10  9   8   | 7   6   5   4   | 3   2   1   0
+        --  --  --  --    --  --  --  --    --  --  --  Rx1           LED LED
+
+    RB  15  14  13  12  | 11  10  9   8   | 7   6   5   4   | 3   2   1   0
+        AN  AN                    Tx2 Rx2   SW          Tx1   SCL SDA
+  */
+  // Setting the Output Latch SFR(s)
+  LATA = 0x0000;
+  LATB = 0x0000;
+
+  // Setting the GPIO Direction SFR(s)
+  TRISA = 0x001C;
+  TRISB = 0xFDE0;
+
+  // Setting the Weak Pull Up and Weak Pull Down SFR(s)
+  CNPDA = 0x000C;
+  CNPDB = 0x3C60;
+
+  CNPUA = 0x0000;
+  CNPUB = 0x0080;
+
+  // Setting the Open Drain SFR(s)
+  ODCA = 0x0000;
+  ODCB = 0x0000;
+
+  // Setting the Analog/Digital Configuration SFR(s)
+  ANSELA = 0x0000;
+  ANSELB = 0xC000;
+
+  /*
+    Oscillator
+  */
+  // set this if you need.
+
+  /*
+    Interrupt
+  */
+  // Enable the multi vector
+  INTCONbits.MVEC = 1;
+  // Enable Global Interrupts
+  __builtin_mtc0(12,0,(__builtin_mfc0(12,0) | 0x0001));
+}
+
+
+/*! onboard LED control.
+
+  @param num	LED number. 1 origin.
+  @param on_off	ON or OFF (True or False)
+*/
+void onboard_led( int num, int on_off )
+{
+  switch( num ) {
+  case 1: LATAbits.LATA0 = !!on_off;	break;
+  case 2: LATAbits.LATA1 = !!on_off;	break;
+  case 3: LATBbits.LATB0 = !!on_off;	break;
+  case 4: LATBbits.LATB1 = !!on_off;	break;
+  }
+}
+
+
+/*! onboard SW control.
+
+  @param num	SW number. 1 origin.
+  @return	1 is OFF, 0 is ON.
+*/
+int onboard_sw( int num )
+{
+  return PORTBbits.RB7;
+}

PIC32MX170F256B/model_dependent.h

@@ -0,0 +1,119 @@
+/*
+  MPU and board model related params.
+
+  PIC32MX170F256B
+
+  CPU clock 40MHz
+   internal oscillator + PLL
+  Peripheral clock 10MHz
+*/
+
+#if !defined(__32MX170F256B__) && !defined(__PIC32MX170F256B__)
+# error "Change the project property, xc32-gcc Include directories to the MPU you want to use."
+#endif
+
+#ifndef MODEL_DEPENDENT_H
+#define MODEL_DEPENDENT_H
+
+#include <xc.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! get offset of port address.
+
+    以下のレジスタが、番号ごとに一定番地離れている事に依存しています。
+      * GPIO 関連のレジスタが、ポートごとに 0x100番地
+      * OC(PWM) 関連のレジスタが、0x200番地
+    そうでないプロセッサに対応が必要になった場合は、戦略の変更が必要です。
+*/
+// Pin settings
+#define ANSELxSET(x)	*(&ANSELASET + (0x100 / sizeof(uint32_t)) * ((x)-1))
+#define ANSELxCLR(x)	*(&ANSELACLR + (0x100 / sizeof(uint32_t)) * ((x)-1))
+#define TRISxSET(x)	*(&TRISASET  + (0x100 / sizeof(uint32_t)) * ((x)-1))
+#define TRISxCLR(x)	*(&TRISACLR  + (0x100 / sizeof(uint32_t)) * ((x)-1))
+#define PORTx(x)	*(&PORTA     + (0x100 / sizeof(uint32_t)) * ((x)-1))
+#define LATxSET(x)	*(&LATASET   + (0x100 / sizeof(uint32_t)) * ((x)-1))
+#define LATxCLR(x)	*(&LATACLR   + (0x100 / sizeof(uint32_t)) * ((x)-1))
+#define ODCxSET(x)	*(&ODCASET   + (0x100 / sizeof(uint32_t)) * ((x)-1))
+#define ODCxCLR(x)	*(&ODCACLR   + (0x100 / sizeof(uint32_t)) * ((x)-1))
+#define CNPUxSET(x)	*(&CNPUASET  + (0x100 / sizeof(uint32_t)) * ((x)-1))
+#define CNPUxCLR(x)	*(&CNPUACLR  + (0x100 / sizeof(uint32_t)) * ((x)-1))
+#define CNPDxSET(x)	*(&CNPDASET  + (0x100 / sizeof(uint32_t)) * ((x)-1))
+#define CNPDxCLR(x)	*(&CNPDACLR  + (0x100 / sizeof(uint32_t)) * ((x)-1))
+
+// Output comparator
+#define NUM_PWM_OC_UNIT 5
+#define OCxCON(x)	*(&OC1CON    + (0x200 / sizeof(uint32_t)) * ((x)-1))
+#define OCxR(x)		*(&OC1R      + (0x200 / sizeof(uint32_t)) * ((x)-1))
+#define OCxRS(x)	*(&OC1RS     + (0x200 / sizeof(uint32_t)) * ((x)-1))
+
+// SPI
+#define NUM_SPI_UNIT 2
+#define SPIxCON(x)	*(&SPI1CON   + (0x200 / sizeof(uint32_t)) * ((x)-1))
+#define SPIxCONSET(x)	*(&SPI1CONSET+ (0x200 / sizeof(uint32_t)) * ((x)-1))
+#define SPIxCONCLR(x)	*(&SPI1CONCLR+ (0x200 / sizeof(uint32_t)) * ((x)-1))
+#define SPIxSTAT(x)	*(&SPI1STAT  + (0x200 / sizeof(uint32_t)) * ((x)-1))
+#define SPIxBUF(x)	*(&SPI1BUF   + (0x200 / sizeof(uint32_t)) * ((x)-1))
+#define SPIxBRG(x)	*(&SPI1BRG   + (0x200 / sizeof(uint32_t)) * ((x)-1))
+#define SPIxCON2(x)	*(&SPI1CON2  + (0x200 / sizeof(uint32_t)) * ((x)-1))
+#define SDIxR(x)	*(&SDI1R     + (0x00c / sizeof(uint32_t)) * ((x)-1))
+
+// UART
+#define NUM_UART_UNIT 2
+#define UxMODE(x)	*(&U1MODE    + (0x200 / sizeof(uint32_t)) * ((x)-1))
+#define UxMODESET(x)	*(&U1MODESET + (0x200 / sizeof(uint32_t)) * ((x)-1))
+#define UxMODECLR(x)	*(&U1MODECLR + (0x200 / sizeof(uint32_t)) * ((x)-1))
+#define UxSTA(x)	*(&U1STA     + (0x200 / sizeof(uint32_t)) * ((x)-1))
+#define UxSTASET(x)	*(&U1STASET  + (0x200 / sizeof(uint32_t)) * ((x)-1))
+#define UxSTACLR(x)	*(&U1STACLR  + (0x200 / sizeof(uint32_t)) * ((x)-1))
+#define UxTXREG(x)	*(&U1TXREG   + (0x200 / sizeof(uint32_t)) * ((x)-1))
+#define UxRXREG(x)	*(&U1RXREG   + (0x200 / sizeof(uint32_t)) * ((x)-1))
+#define UxBRG(x)	*(&U1BRG     + (0x200 / sizeof(uint32_t)) * ((x)-1))
+#define UxRXR(x)	*(&U1RXR     + (0x008 / sizeof(uint32_t)) * ((x)-1))
+#define IPC_U1IPIS(ip,is)	(IPC8bits.U1IP = (ip), IPC8bits.U1IS = (is))
+#define IPC_U2IPIS(ip,is)	(IPC9bits.U2IP = (ip), IPC9bits.U2IS = (is))
+
+// Output pin selection.
+#define RPxnR(x,n)	(TBL_RPxnR[(x)-1][n])
+extern volatile uint32_t *TBL_RPxnR[];
+
+/*! default pin assign.
+*/
+// UART
+#define UART1_TXD_PIN	2,4     // B4
+#define UART1_RXD_PIN	1,4     // A4
+#define UART2_TXD_PIN	2,9	// B9
+#define UART2_RXD_PIN	2,8	// B8
+#define UART_CONSOLE	1
+
+// flash memory address and parameter.
+#define FLASH_SAVE_ADDR 0xBD035000
+#define FLASH_END_ADDR  0xBD03EFFF
+#define FLASH_PAGE_SIZE 1024
+#define FLASH_ROW_SIZE (FLASH_PAGE_SIZE / 8)
+#define FLASH_ALIGN_ROW_SIZE(bytes) \
+  ((((bytes)-1) / FLASH_ROW_SIZE + 1) * FLASH_ROW_SIZE)
+
+
+// System clock.
+#if !defined(_XTAL_FREQ)
+#define _XTAL_FREQ  40000000UL
+#endif
+
+#if !defined(PBCLK)
+#define PBCLK (_XTAL_FREQ / 4)
+#endif
+
+
+void system_init(void);
+void onboard_led(int num, int on_off);
+int onboard_sw(int num);
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif  /* MODEL_DEPENDENT_H */