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RP2040 SPI HAL Improvements #222
RP2040 SPI HAL Improvements #222
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Looks pretty good so far. Do we need clock_config
to be comptime
known. If not, we can remove the comptime config
requirement on the apply
fn
@ikskuh Requested changes applied! |
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In general, i'm pretty happy now. Can you maybe add an example where you use a non-u8 type for data width?
For sure! I'll add an example then merge :) |
- Added support for all SPI modes + bit widths - Implemented TX FIFO "pre-loading" for improved performance
…checks - Other minor odds and ends per PR review
- Changed num() to from_instance_number() for clarity - Added support for all SPI modes + bit widths - Implemented TX FIFO "pre-loading" for improved performance - Update example with SPI - Renamed functions to _blocking for consistency among HALs - Changed instance access style - Changed data_width to DataWidthBits to reduce confusion + need for checks - Other minor odds and ends per PR review - Added example of using data width other than 8
Relatively minor improvements, but the highlights:
Example transaction before:
Example transaction with preloading (no gap!):
CSN
pin automatically is a bit odd, it toggles CSN high after every byte when a GPIO is configured to.spi
function:- For the flash chip I tested this driver on, this would actually make it unusable was I forced to use this
- Instead, I manually drive CSN via a GPIO, which works perfectly well
- Not configuring the GPIOs within the peripheral driver gives users of the HAL this kind of flexibility
The full test suite I wrote for this driver can be found here:
https://github.com/haydenridd/microzig/tree/rp2040-spi