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Added a test for all sizes 32/64b and alignments
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Signed-off-by: Anderson Ignacio <anderson@aignacio.com>
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aignacio committed Dec 25, 2023
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4 changes: 2 additions & 2 deletions cocotbext/ahb/ahb_master.py
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Expand Up @@ -4,7 +4,7 @@
# License : MIT license <Check LICENSE>
# Author : Anderson I. da Silva (aignacio) <anderson@aignacio.com>
# Date : 08.10.2023
# Last Modified Date: 15.11.2023
# Last Modified Date: 25.12.2023

import cocotb
import logging
Expand Down Expand Up @@ -184,7 +184,7 @@ async def _send_txn(
f"\tID = {index}\n"
f"\tADDR = 0x{txn_addr:x}\n"
f"\tDATA = 0x{value[index+1]:x}\n"
f"\tSIZE = {txn_size}"
f"\tSIZE = {txn_size} bytes"
)
self.bus.hwdata.value = txn_data
if self.bus.hready_in_exist:
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123 changes: 86 additions & 37 deletions docs_utils/template_64b.gtkw
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[*]
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
[*] Mon Oct 30 18:55:22 2023
[*] Mon Dec 25 19:36:33 2023
[*]
[dumpfile] "run_dir/sim_build_icarus_test_ahb_lite_sram_data_width_64_bits/ahb_template.fst"
[dumpfile_mtime] "Mon Oct 30 18:52:23 2023"
[dumpfile_size] 123189
[dumpfile] "./run_dir/sim_build_icarus_test_ahb_lite_sram_all_sizes_data_width_64_bits/ahb_template.fst"
[dumpfile_mtime] "Mon Dec 25 19:32:54 2023"
[dumpfile_size] 1768
[savefile] "/Users/aignacio/projects/cocotbext-ahb/docs_utils/template_64b.gtkw"
[timestart] 0
[size] 1440 771
[pos] 577 0
*-25.811741 18043200 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[size] 3008 1554
[pos] 1890 802
*-16.359070 103180 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[sst_width] 253
[signals_width] 315
[sst_expanded] 1
[sst_vpaned_height] 252
[sst_vpaned_height] 566
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@1401201
-group_end
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86 changes: 34 additions & 52 deletions tests/test_ahb_lite_sram_all_sizes.py
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Expand Up @@ -3,7 +3,7 @@
# License : MIT license <Check LICENSE>
# Author : Anderson I. da Silva (aignacio) <anderson@aignacio.com>
# Date : 08.10.2023
# Last Modified Date: 18.12.2023
# Last Modified Date: 25.12.2023

import cocotb
import os
Expand All @@ -15,10 +15,21 @@
from cocotb_test.simulator import run
from cocotb.triggers import ClockCycles
from cocotb.clock import Clock
from cocotbext.ahb import AHBBus, AHBLiteMaster, AHBLiteSlaveRAM, AHBResp, AHBMonitor
from cocotbext.ahb import (
AHBBus,
AHBLiteMaster,
AHBLiteSlaveRAM,
AHBResp,
AHBMonitor,
AHBSize,
)
from cocotb.regression import TestFactory


def get_rnd_addr(mem_size_kib: int = 0):
return random.randint(0, ((mem_size_kib - 1) * 1024) - 1) & 0xFFFF_FFF8


def rnd_val(bit: int = 0, zero: bool = True):
if zero is True:
return random.randint(0, (2**bit) - 1)
Expand Down Expand Up @@ -58,13 +69,7 @@ async def run_test(dut, bp_fn=None, pip_mode=False):
ahb_bus_slave = AHBBus.from_entity(dut)

data_width = ahb_bus_slave.data_width

await setup_dut(dut, cfg.RST_CYCLES)

ahb_lite_mon = AHBMonitor(ahb_bus_slave, dut.hclk, dut.hresetn)

# Below is only required bc of flake8 - non-used rule
type(ahb_lite_mon)
n_bytes = data_width // 8

ahb_lite_sram = AHBLiteSlaveRAM(
AHBBus.from_entity(dut),
Expand All @@ -82,49 +87,26 @@ async def run_test(dut, bp_fn=None, pip_mode=False):
AHBBus.from_entity(dut), dut.hclk, dut.hresetn, def_val="Z"
)

# Generate a list of unique addresses with the double of memory size
# to create error responses
address = random.sample(range(0, 2 * mem_size_kib * 1024, 8), N)
# Generate a list of random 32-bit values
value = [rnd_val(data_width) for _ in range(N)]
# Generate a list of random sizes
if data_width == 32:
size = [pick_random_value([1, 2, 4]) for _ in range(N)]
else:
size = [pick_random_value([1, 2, 4, 8]) for _ in range(N)]

# Create the comparison list with expected results
expected = []
for addr, val, sz in zip(address, value, size):
resp, data = 0, 0
if addr >= mem_size_kib * 1024:
resp = AHBResp.ERROR
else:
resp = AHBResp.OKAY
if sz == 1:
data = val & 0xFF
elif sz == 2:
data = val & 0xFFFF
elif sz == 4:
data = val & 0xFFFFFFFF
elif sz == 8:
data = val & 0xFFFFFFFFFFFFFFFF
expected.append({"resp": resp, "data": hex(data)})

# Perform the writes and reads
resp = await ahb_lite_master.write(address, value, size, pip=pip_mode)
resp = await ahb_lite_master.read(address, size, pip=pip_mode)
print(resp)
# Compare all txns
for index, (real, expect) in enumerate(zip(resp, expected)):
if real != expect:
print("------ERROR------")
print(f"Txn ID: {index}")
print("DUT")
print(real)
print("Expected")
print(expect)
assert real == expect, "DUT != Expected"
await setup_dut(dut, cfg.RST_CYCLES)

seq_ops = [1, 2, 4] if data_width == 32 else [1, 2, 4, 8]
mask = [0xFF, 0xFFFF, 0xFFFF_FFFF, 0xFFFF_FFFF_FFFF_FFFF]

for index, byte_mode in enumerate(seq_ops):
address_dw_aligned = get_rnd_addr(mem_size_kib)
addr = [address_dw_aligned + i for i in range(0, n_bytes, byte_mode)]
data = [rnd_val(data_width, False) for i in range(len(addr))]
size = [byte_mode for i in range(len(addr))]
resp_wr = await ahb_lite_master.write(addr, data, size, pip=pip_mode)
print(resp_wr)
expect = sum(
(data[i // byte_mode] & mask[index]) << (8 * i)
for i in range(0, n_bytes, byte_mode)
)
resp_rd = await ahb_lite_master.read(address_dw_aligned, pip=pip_mode)
assert (
hex(expect) == resp_rd[0]["data"]
), f"Mismatch between WR/RD {hex(expect)} != {resp_rd[0]['data']}"


if cocotb.SIM_NAME:
Expand Down

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