Included 32b/64b data width testing on slave ahb RAM

Signed-off-by: Anderson Ignacio <anderson@aignacio.com>

cocotbext/ahb/version.py

@@ -1 +1 @@
-__version__ = "0.1.2"
+__version__ = "0.1.3"

docs_utils/template_64b.gtkw

@@ -0,0 +1,57 @@
+[*]
+[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
+[*] Mon Oct 30 18:55:22 2023
+[*]
+[dumpfile] "run_dir/sim_build_icarus_test_ahb_lite_sram_data_width_64_bits/ahb_template.fst"
+[dumpfile_mtime] "Mon Oct 30 18:52:23 2023"
+[dumpfile_size] 123189
+[savefile] "/Users/aignacio/projects/cocotbext-ahb/docs_utils/template_64b.gtkw"
+[timestart] 0
+[size] 1440 771
+[pos] 577 0
+*-25.811741 18043200 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 253
+[signals_width] 315
+[sst_expanded] 1
+[sst_vpaned_height] 252
+@28
+ahb_template.hresetn
+ahb_template.hclk
+@200
+-
+-slave
+@28
+ahb_template.slave_hsel
+@22
+ahb_template.slave_haddr[31:0]
+@28
+ahb_template.slave_hsize[2:0]
+ahb_template.slave_htrans[1:0]
+ahb_template.slave_hwrite
+@23
+ahb_template.slave_hwdata[63:0]
+@28
+ahb_template.slave_hready_in
+ahb_template.slave_hready
+ahb_template.slave_hresp
+@22
+ahb_template.slave_hrdata[63:0]
+@200
+-
+-master
+@22
+ahb_template.master_haddr[31:0]
+@28
+ahb_template.master_hsize[2:0]
+ahb_template.master_htrans[1:0]
+ahb_template.master_hwrite
+@22
+ahb_template.master_hwdata[63:0]
+@28
+ahb_template.master_hready_in
+ahb_template.master_hready
+ahb_template.master_hresp
+@22
+ahb_template.master_hrdata[63:0]
+[pattern_trace] 1
+[pattern_trace] 0

tests/test_ahb_lite_sram.py

@@ -3,12 +3,13 @@
 # License           : MIT license <Check LICENSE>
 # Author            : Anderson I. da Silva (aignacio) <anderson@aignacio.com>
 # Date              : 08.10.2023
-# Last Modified Date: 27.10.2023
+# Last Modified Date: 30.10.2023
 
 import cocotb
 import os
 import random
 import math
+import pytest
 
 from const import cfg
 from cocotb_test.simulator import run
@@ -51,15 +52,16 @@ async def setup_dut(dut, cycles):
 
 @cocotb.test()
 async def run_test(dut, bp_fn=None, pip_mode=False):
-    data_width = 32
     mem_size_kib = 16
     N = 1000
 
+    ahb_bus_slave = AHBBus.from_prefix(dut, "slave")
+
+    data_width = ahb_bus_slave.data_width
+
     await setup_dut(dut, cfg.RST_CYCLES)
 
-    ahb_lite_mon = AHBMonitor(
-        AHBBus.from_prefix(dut, "slave"), dut.hclk, dut.hresetn
-    )
+    ahb_lite_mon = AHBMonitor(ahb_bus_slave, dut.hclk, dut.hresetn)
 
     # Below is only required bc of flake8 - non-used rule
     type(ahb_lite_mon)
@@ -86,7 +88,10 @@ async def run_test(dut, bp_fn=None, pip_mode=False):
     # Generate a list of random 32-bit values
     value = [rnd_val(data_width) for _ in range(N)]
     # Generate a list of random sizes
-    size = [pick_random_value([1, 2, 4]) for _ in range(N)]
+    if data_width == 32:
+        size = [pick_random_value([1, 2, 4]) for _ in range(N)]
+    else:
+        size = [pick_random_value([1, 2, 4, 8]) for _ in range(N)]
 
     # Create the comparison list with expected results
     expected = []
@@ -131,15 +136,17 @@ async def run_test(dut, bp_fn=None, pip_mode=False):
     factory.generate_tests()
 
 
-def test_ahb_lite_sram():
+@pytest.mark.parametrize("data_width", [{"DATA_WIDTH": "32"}, {"DATA_WIDTH": "64"}])
+def test_ahb_lite_sram(data_width):
     """
     Test AHB lite SRAM
 
     Test ID: 3
     """
     module = os.path.splitext(os.path.basename(__file__))[0]
     SIM_BUILD = os.path.join(
-        cfg.TESTS_DIR, f"../run_dir/sim_build_{cfg.SIMULATOR}_{module}"
+        cfg.TESTS_DIR,
+        f"../run_dir/sim_build_{cfg.SIMULATOR}_{module}_data_width_{data_width['DATA_WIDTH']}_bits",
     )
     extra_args_sim = cfg.EXTRA_ARGS
 
@@ -148,6 +155,7 @@ def test_ahb_lite_sram():
         verilog_sources=cfg.VERILOG_SOURCES,
         toplevel=cfg.TOPLEVEL,
         module=module,
+        parameters=data_width,
         sim_build=SIM_BUILD,
         extra_args=extra_args_sim,
         extra_env=cfg.EXTRA_ENV,