- Auto generate a concrete C++ implementation of the SystemVerilog (VHDL in future) Object Model following the IEEE standard object model
- Auto generate a standard VPI interface as a facade to the C++ model
- Auto generate a serialization/deserialization of the data model
- Auto generate a Visitor (Walker) function that exercise the entire VPI interface (used in uhdm-dump executable)
- Auto generate a C++ Listener Design Pattern that traverse the entire VPI data model (used in uhdm-listener executable)
- Auto generate an Elaborator that uniquifies nets, variables...
- The generated Object Model can, for a given design, be:
* git clone https://github.com/alainmarcel/UHDM.git
* cd UHDM
* git submodule update --init --recursive
* make- All SystemVerilog models are expressed in a Yaml type syntax (One file per Verilog Object Model)
- From this Yaml description, all the code (C++ headers, VPI Interface, Serialization) is automatically generated.
- Model inheritance and object/class grouping is supported (To follow the IEEE standard)
- Supports the concept of "design" on top of the IEEE standard to support partitioning and multi-language (SystemVerilog - VHDL)
- Any deviation/addition from the standard is cleary indicated by a uhdm prefix, IEEE standard API is either prefixed by vpi (Verilog) or vhpi (VHDL).