Add baremetal target with support for 32bit RPI4

Cargo.toml

@@ -3,7 +3,8 @@ members = [
     "gb",
     "lib_gb",
     "image_inter",
-    "bcm_host"
+    "bcm_host",
+    "baremetal"
 ]
 
 [workspace.package]

baremetal/.cargo/config.toml

@@ -0,0 +1,6 @@
+[build]
+target = "armv7a-none-eabihf"
+rustflags = [
+    "-Clink-arg=--script=./baremetal/link.ld", 
+    "-Ctarget-feature=+virtualization"
+]

baremetal/Cargo.toml

@@ -0,0 +1,17 @@
+[package]
+name = "baremetal"
+version.workspace = true
+authors.workspace = true
+edition = "2021"
+
+# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
+
+[dependencies]
+log = "0.4"
+lib_gb = {path = "../lib_gb", features = ["u16pixel"]}
+image_inter = {path = "../image_inter"}
+
+[features]
+default = ["rpi4"]
+rpi4 = []
+rpi2 = []

baremetal/build.bat

@@ -0,0 +1,2 @@
+cargo +nightly b -r -Z build-std=core
+rust-objcopy ../target/armv7a-none-eabihf/release/baremetal -O binary kernel7.img

baremetal/build.rs

@@ -0,0 +1,5 @@
+const LD_SCRIPT_PATH:&str = "link.ld";
+
+fn main(){
+    println!("cargo:rerun-if-changed={}", LD_SCRIPT_PATH);
+}

baremetal/build.sh

@@ -0,0 +1,3 @@
+# armv7a-none-eabihf is not supported automacticaly by rust so the nightly toolchain is neccessary to build the core library
+cargo +nightly b -r -Z build-std=core
+rust-objcopy ../target/armv7a-none-eabihf/release/baremetal -O binary kernel7.img

baremetal/config.txt

@@ -0,0 +1,7 @@
+# configuration for the RPI
+arm_64bit=0 # boot to 32 bit mode
+
+# fast boot
+boot_delay=0
+disable_poe_fan=1
+disable_splash=1

baremetal/link.ld

@@ -0,0 +1,60 @@
+/* Place _start procedure at the entry address for RPI */
+__rpi_32_phys_binary_load_addr = 0x8000;
+__isr_table_addr = 0;
+__stack_size = 0x100000; /* 1MB stack */
+ENTRY(__rpi_32_phys_binary_load_addr)   /* enry point */
+
+SECTIONS
+{
+    .isr_table (NOLOAD) :  
+    {
+        . = __isr_table_addr;
+        /* allocate space for the table */
+        . = . + 0x40;
+    }
+    . = __rpi_32_phys_binary_load_addr;
+    .text : 
+    {
+        KEEP(*(.text._start)) /*put _start first, `KEEP` disables linker optimizations*/
+        *(.text*)
+    }
+    /*readonly data - readonly global variables*/
+    .rodata :
+    {
+        *(.rodata*)
+    }
+    /*global variables*/
+    .data :
+    {
+        *(.data*)
+    }
+    .stack (NOLOAD) : ALIGN(16)
+    {
+        . = . + __stack_size;
+        __cpu0_stack_start = .; /* stack grows from high address to low address */
+    }
+    /*bss must be at the end of the linker script in order to keep the image small (otherwise objcopy will gap the space between bss and the next section)*/
+    /*uninitialized global variables*/
+    .bss (NOLOAD) : ALIGN(16)
+    {
+        __bss_start = .;
+        *(.bss*)
+        __bss_end = .;
+    }
+    /* uncached memory - used by drivers and devices */
+    /* Since L1 memory map entry is 1MB, make sure it's alligned correctly*/
+    .uncached (NOLOAD) : ALIGN(0x100000)
+    {
+        __uncached_data_start = .;
+        __cached_data_map_size = __uncached_data_start / 0x100000;
+        *(.uncached*)
+    }
+
+    /* Remove those sections from the final binary */
+    /DISCARD/ : 
+    {
+        *(.ARM.attributes)
+        *(.ARM.exidx) /* Used for stack unwinding - not relevant for now */  
+        *(.comment) /* comments about the compiler and linker - not intresting */
+    }
+}

baremetal/src/boot.rs

@@ -0,0 +1,18 @@
+use core::arch::{global_asm, asm};
+
+#[no_mangle]
+static PERIPHERALS_BASE_ADDRESS:u32 = crate::peripherals::PERIPHERALS_BASE_ADDRESS as u32;
+
+global_asm!(include_str!("boot_armv7a.s"));
+
+extern "C"{
+    // declared at startup assembly file
+    pub fn hang_led()->!;
+}
+
+pub fn get_cpu_execution_mode()->u32{
+    let mut mode:u32;
+    unsafe{asm!("mrs {r}, cpsr", r = out(reg) mode)};
+    // only the first 5 bits are relevant for the mode
+    return mode & 0b1_1111;
+}