update BARs and Telemetry #248
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Signed-off-by: Min Ma <min.ma@amd.com>
maxzhen
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sonals
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sonals
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src/driver/doc/amdnpu.rst
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| * On NPU1 device, PSP, SMU, Public Register BARs are on PCIe BAR index 0. | ||
| * On NPU4 device, Mailbox and Public Register BARs are on PCIe BAR index 0. | ||
| The PSP BAR has some registers in PCIe BAR index 0 and PCIe BAR index 4. |
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Should we change PSP BAR to PSP and say:
The PSP has has some registers in PCIe BAR index 0 and PCIe BAR index 4.
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Because in the bullet item list, I use "PSP BAR", "SMU BAR". Maybe I should said,
A module might require two physical PCIe BARs to be fully functional.
...
The PSP has has some registers in PCIe BAR index 0 (Public Register BAR) and PCIe BAR index 4 (PSP BAR).
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Signed-off-by: Min Ma <min.ma@amd.com>
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Signed-off-by: Min Ma <min.ma@amd.com>
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