Second pr test

README.md

@@ -1,5 +1,5 @@
 # AMD XDNA™️ Driver for Linux®️
-This repository is for the AMD XDNA™️ Driver (amdxdna.ko) for Linux®️ and XRT SHIM library development.
+This repository is for the AMD XDNA™️ Driver (amdxdna.ko) for Linux®️ and XRT SHIM library development..
 
 ## Table of Contents
 - [Introduction](#introduction)
@@ -88,7 +88,7 @@ cd <root-of-source-tree>/build
 cd xrt/build
 ./build.sh -noert -noalveo
 # To adapt according to your OS & version
-sudo apt reinstall ./Release/xrt_202410.2.17.0_23.10-amd64-xrt.deb ./Release/xrt_202410.2.17.0_23.10-amd64-xbflash2.deb
+sudo apt reinstall ./Release/xrt_202410.2.17.0_23.10-amd64-xrt.deb
 cd ../../build
 
 # Start XDNA driver release build

WHENCE

@@ -11,5 +11,6 @@ File:
 	tools/bins/1502_00/validate.xclbin
 	tools/bins/17f0_10/validate.xclbin
 	tools/bins/17f0_11/validate.xclbin
+	tools/bins/17f0_20/validate.xclbin
 
 Licence: Redistributable. See LICENSE.amdnpu for details.

src/driver/CMakeLists.txt

@@ -92,6 +92,8 @@ install(FILES ${CMAKE_CURRENT_BINARY_DIR}/dkms.conf
 
 set(amdxdna_drv_tools
   ${CMAKE_CURRENT_SOURCE_DIR}/tools/dkms_driver.sh
+  ${CMAKE_CURRENT_SOURCE_DIR}/tools/npu_perf_trace.sh
+  ${CMAKE_CURRENT_SOURCE_DIR}/tools/npu_perf_analyze.sh
   )
 install(FILES ${amdxdna_drv_tools}
   PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE GROUP_READ GROUP_EXECUTE WORLD_READ WORLD_EXECUTE

src/driver/amdxdna/aie2_ctx.c

@@ -47,21 +47,13 @@ aie2_hwctx_get_job(struct amdxdna_hwctx *hwctx, u64 seq)
 {
 	int idx;
 
-	/* Special sequence number for oldest fence if exist */
-	if (seq == AMDXDNA_INVALID_CMD_HANDLE) {
-		idx = get_job_idx(hwctx->submitted);
-		goto out;
-	}
-
 	if (seq >= hwctx->submitted)
 		return ERR_PTR(-EINVAL);
 
 	if (seq + HWCTX_MAX_CMDS < hwctx->submitted)
 		return NULL;
 
 	idx = get_job_idx(seq);
-
-out:
 	return hwctx->priv->pending[idx];
 }
 
@@ -230,8 +222,8 @@ aie2_sched_notify(struct amdxdna_sched_job *job)
 	struct dma_fence *fence = job->fence;
 
 	job->hwctx->completed++;
+	trace_xdna_job(&job->base, job->hwctx->name, "signaling fence", job->seq);
 	dma_fence_signal(fence);
-	trace_xdna_job(&job->base, job->hwctx->name, "signaled fence", job->seq);
 	dma_fence_put(fence);
 	mmput(job->mm);
 	amdxdna_job_put(job);
@@ -257,7 +249,7 @@ aie2_sched_resp_handler(void *handle, const u32 *data, size_t size)
 	}
 
 	status = *data;
-	XDNA_DBG(job->hwctx->client->xdna, "Resp status 0x%x", status);
+	XDNA_DBG(job->hwctx->client->xdna, "Response status 0x%x", status);
 	if (status == AIE2_STATUS_SUCCESS)
 		amdxdna_cmd_set_state(cmd_abo, ERT_CMD_STATE_COMPLETED);
 	else
@@ -284,7 +276,7 @@ aie2_sched_nocmd_resp_handler(void *handle, const u32 *data, size_t size)
 	}
 
 	status = *data;
-	XDNA_DBG(job->hwctx->client->xdna, "Resp status 0x%x", status);
+	XDNA_DBG(job->hwctx->client->xdna, "Response status 0x%x", status);
 
 out:
 	aie2_sched_notify(job);
@@ -540,6 +532,7 @@ int aie2_hwctx_init(struct amdxdna_hwctx *hwctx)
 	struct drm_gpu_scheduler *sched;
 	struct amdxdna_hwctx_priv *priv;
 	struct amdxdna_gem_obj *heap;
+	unsigned int wq_flags;
 	int i, ret;
 
 	priv = kzalloc(sizeof(*hwctx->priv), GFP_KERNEL);
@@ -587,12 +580,21 @@ int aie2_hwctx_init(struct amdxdna_hwctx *hwctx)
 
 	sched = &priv->sched;
 	mutex_init(&priv->io_lock);
-	ret = drm_sched_init(sched, &sched_ops, NULL, DRM_SCHED_PRIORITY_COUNT,
+
+	wq_flags = __WQ_ORDERED;
+	if (!aie2_pm_is_turbo(xdna->dev_handle))
+		wq_flags |= WQ_UNBOUND;
+	priv->submit_wq = alloc_workqueue(hwctx->name, wq_flags, 1);
+	if (!priv->submit_wq) {
+		XDNA_ERR(xdna, "Failed to alloc submit wq");
+		goto free_cmd_bufs;
+	}
+	ret = drm_sched_init(sched, &sched_ops, priv->submit_wq, DRM_SCHED_PRIORITY_COUNT,
 			     HWCTX_MAX_CMDS, 0, MAX_SCHEDULE_TIMEOUT,
 			     NULL, NULL, hwctx->name, xdna->ddev.dev);
 	if (ret) {
 		XDNA_ERR(xdna, "Failed to init DRM scheduler. ret %d", ret);
-		goto free_cmd_bufs;
+		goto free_wq;
 	}
 
 	ret = drm_sched_entity_init(&priv->entity, DRM_SCHED_PRIORITY_NORMAL,
@@ -645,6 +647,8 @@ int aie2_hwctx_init(struct amdxdna_hwctx *hwctx)
 	drm_sched_entity_destroy(&priv->entity);
 free_sched:
 	drm_sched_fini(&priv->sched);
+free_wq:
+	destroy_workqueue(priv->submit_wq);
 free_cmd_bufs:
 	for (i = 0; i < ARRAY_SIZE(priv->cmd_buf); i++) {
 		if (!priv->cmd_buf[i])
@@ -681,6 +685,7 @@ void aie2_hwctx_fini(struct amdxdna_hwctx *hwctx)
 	aie2_hwctx_wait_for_idle(hwctx);
 	drm_sched_entity_destroy(&hwctx->priv->entity);
 	drm_sched_fini(&hwctx->priv->sched);
+	destroy_workqueue(hwctx->priv->submit_wq);
 
 	for (idx = 0; idx < HWCTX_MAX_CMDS; idx++) {
 		job = hwctx->priv->pending[idx];
@@ -928,7 +933,7 @@ int aie2_cmd_submit(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job,
 	job->out_fence = dma_fence_get(&job->base.s_fence->finished);
 
 retry:
-	ret = drm_gem_lock_reservations(job->bos, job->bo_cnt, &acquire_ctx);
+	ret = amdxdna_lock_objects(job, &acquire_ctx);
 	if (ret) {
 		XDNA_WARN(xdna, "Failed to reverve fence, ret %d", ret);
 		goto put_fence;
@@ -937,7 +942,7 @@ int aie2_cmd_submit(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job,
 	for (i = 0; i < job->bo_cnt; i++) {
 		abo = to_xdna_obj(job->bos[i]);
 		if (abo->mem.map_invalid) {
-			drm_gem_unlock_reservations(job->bos, job->bo_cnt, &acquire_ctx);
+			amdxdna_unlock_objects(job, &acquire_ctx);
 			if (!timeout) {
 				timeout = jiffies +
 					msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
@@ -955,19 +960,27 @@ int aie2_cmd_submit(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job,
 		ret = dma_resv_reserve_fences(job->bos[i]->resv, 1);
 		if (ret) {
 			XDNA_WARN(xdna, "Failed to reserve fences %d", ret);
-			drm_gem_unlock_reservations(job->bos, job->bo_cnt, &acquire_ctx);
+			amdxdna_unlock_objects(job, &acquire_ctx);
 			goto put_fence;
 		}
 	}
 
 	for (i = 0; i < job->bo_cnt; i++)
 		dma_resv_add_fence(job->bos[i]->resv, job->out_fence, DMA_RESV_USAGE_WRITE);
-	drm_gem_unlock_reservations(job->bos, job->bo_cnt, &acquire_ctx);
+	amdxdna_unlock_objects(job, &acquire_ctx);
 
+again:
 	mutex_lock(&hwctx->priv->io_lock);
 	ret = aie2_hwctx_add_job(hwctx, job);
 	if (ret) {
 		mutex_unlock(&hwctx->priv->io_lock);
+
+		if (ret == -EAGAIN) {
+			// Waiting for the first pending cmd to complete before trying again.
+			int res = aie2_cmd_wait(hwctx, hwctx->submitted - HWCTX_MAX_CMDS, 0);
+			if (!res)
+				goto again;
+		}
 		goto signal_fence;
 	}
 

src/driver/amdxdna/aie2_debugfs.c

@@ -77,71 +77,6 @@ static int aie2_dbgfs_entry_release(struct inode *inode, struct file *file)
 #define file_to_ndev_rw(file) \
 	(((struct seq_file *)(file)->private_data)->private)
 
-static ssize_t
-aie2_dbgfs_clock_write(struct amdxdna_dev_hdl *ndev, struct clock *clock,
-		       const char __user *ptr, size_t len, loff_t *off)
-{
-	u32 val;
-	int ret;
-
-	ret = kstrtouint_from_user(ptr, len, 10, &val);
-	if (ret) {
-		XDNA_ERR(ndev->xdna, "Invalid input value: %d", val);
-		return ret;
-	}
-
-	clock->dbg_freq_mhz = val;
-	if (!clock->dbg_freq_mhz) {
-		XDNA_INFO(ndev->xdna, "Auto %s", clock->name);
-		return 0;
-	}
-
-	ret = aie2_smu_set_clock_freq(ndev, clock, val);
-	if (ret) {
-		clock->dbg_freq_mhz = 0;
-		XDNA_ERR(ndev->xdna, "Set %s ret %d, use auto clock", clock->name, ret);
-		return ret;
-	}
-
-	return len;
-}
-
-static ssize_t aie2_dbgfs_mpnpu_clock_write(struct file *file, const char __user *ptr,
-					    size_t len, loff_t *off)
-{
-	struct amdxdna_dev_hdl *ndev = file_to_ndev_rw(file);
-
-	return aie2_dbgfs_clock_write(ndev, &ndev->smu.mp_npu_clock, ptr, len, off);
-}
-
-static int aie2_dbgfs_mpnpu_clock_show(struct seq_file *m, void *unused)
-{
-	struct amdxdna_dev_hdl *ndev = m->private;
-
-	seq_printf(m, "%d\n", aie2_smu_get_mpnpu_clock_freq(ndev));
-	return 0;
-}
-
-AIE2_DBGFS_FOPS(npuclock, aie2_dbgfs_mpnpu_clock_show, aie2_dbgfs_mpnpu_clock_write);
-
-static ssize_t aie2_dbgfs_hclock_write(struct file *file, const char __user *ptr,
-				       size_t len, loff_t *off)
-{
-	struct amdxdna_dev_hdl *ndev = file_to_ndev_rw(file);
-
-	return aie2_dbgfs_clock_write(ndev, &ndev->smu.h_clock, ptr, len, off);
-}
-
-static int aie2_dbgfs_hclock_show(struct seq_file *m, void *unused)
-{
-	struct amdxdna_dev_hdl *ndev = m->private;
-
-	seq_printf(m, "%d\n", aie2_smu_get_hclock_freq(ndev));
-	return 0;
-}
-
-AIE2_DBGFS_FOPS(hclock, aie2_dbgfs_hclock_show, aie2_dbgfs_hclock_write);
-
 static ssize_t aie2_pasid_write(struct file *file, const char __user *ptr,
 				size_t len, loff_t *off)
 {
@@ -291,7 +226,7 @@ static ssize_t aie2_dpm_level_set(struct file *file, const char __user *ptr,
 		return ret;
 	}
 
-	ret = aie2_smu_set_dpm_level(ndev, val, true);
+	ret = aie2_smu_set_dpm_level(ndev, val);
 	if (ret) {
 		XDNA_ERR(ndev->xdna, "Setting dpm_level:%d failed, ret: %d", val, ret);
 		return ret;
@@ -302,8 +237,24 @@ static ssize_t aie2_dpm_level_set(struct file *file, const char __user *ptr,
 static int aie2_dpm_level_get(struct seq_file *m, void *unused)
 {
 	struct amdxdna_dev_hdl *ndev = m->private;
+	const struct dpm_clk *dpm_table;
+	u32 num_dpm_levels;
+	int dpm_level;
+	int i;
 
-	seq_printf(m, "%d\n", aie2_smu_get_dpm_level(ndev));
+	dpm_table = SMU_DPM_TABLE_ENTRY(ndev, 0);
+	dpm_level = aie2_smu_get_dpm_level(ndev);
+	num_dpm_levels = SMU_DPM_MAX(ndev);
+	for (i = 0; i <= num_dpm_levels; i++) {
+		u32 npuclk = dpm_table[i].npuclk;
+		u32 hclk = dpm_table[i].hclk;
+
+		if (dpm_level == i)
+			seq_printf(m, " [%d,%d] ", npuclk, hclk);
+		else
+			seq_printf(m, " %d,%d ", npuclk, hclk);
+	}
+	seq_puts(m, "\n");
 	return 0;
 }
 
@@ -511,8 +462,6 @@ seq_printf(m, "%ld:%s\n", _name, #_name)
 	drm_ioctl_id_seq_print(DRM_IOCTL_AMDXDNA_WAIT_CMD);
 	drm_ioctl_id_seq_print(DRM_IOCTL_AMDXDNA_GET_INFO);
 	drm_ioctl_id_seq_print(DRM_IOCTL_AMDXDNA_SET_STATE);
-	drm_ioctl_id_seq_print(DRM_IOCTL_AMDXDNA_SUBMIT_SIGNAL);
-	drm_ioctl_id_seq_print(DRM_IOCTL_AMDXDNA_SUBMIT_WAIT);
 
 	drm_ioctl_id_seq_print(DRM_IOCTL_GEM_CLOSE);
 	drm_ioctl_id_seq_print(DRM_IOCTL_PRIME_HANDLE_TO_FD);
@@ -609,8 +558,6 @@ const struct {
 	umode_t mode;
 } aie2_dbgfs_files[] = {
 	AIE2_DBGFS_FILE(nputest, 0600),
-	AIE2_DBGFS_FILE(hclock, 0600),
-	AIE2_DBGFS_FILE(npuclock, 0600),
 	AIE2_DBGFS_FILE(pasid, 0600),
 	AIE2_DBGFS_FILE(state, 0600),
 	AIE2_DBGFS_FILE(powerstate, 0600),