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M2k DAC buffer fixes #1180

Merged
merged 2 commits into from
Dec 12, 2023
Merged

M2k DAC buffer fixes #1180

merged 2 commits into from
Dec 12, 2023

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AndreiGrozav
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@AndreiGrozav AndreiGrozav commented Sep 22, 2023 •
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PR Description

With this PR we should solve two issues regarding spikes on the DAC(waveform generator)

  1. When using cyclic buffers. The DMA is not stopped by disabling the transfer through its regmap, but from setting the dma_transfer_suspend flag in the axi_dac_interpolate(dma data consumer). This is done in order to start/stop the data synchronously for both channels. When a DMA is stopped, in this manner, valid data will remain in it's internal FIFO. Without flushing it, that data will be part of the first samples from the next transmission.
  2. When not using last sample hold. The output data was grounded, if the data source is not valid. This will cause a spike(few samples from previous buffer) at the beginning and the end of buffers that don't end with zero values.

The last sample_hold will be the default option, useful only for non-cyclic buffers.

Software considerations:

Linux:

The Driver should expose the new flags from register 0x50 and from register 0x64 the attributes for raw data.

libm2k:

The FLUSH_DMA flag is active by default. At this moment we do not plan to use the "pause" feature, so, nothing to be done here. Maybe expose this attribute for advanced users.
Same for STOP_SYNC_CHANNELS.
CH_A_RAW_TRANSFER_EN and CH_A_RAW_DATA should be accessible to users.

When a hold value is desired, after a cyclic buffer there are two option:

  1. If both channels are enabled and dma_transfer_suspend(dma_sync) is used, the last sample will automatically be set from the raw reg value.
  2. When only one channel is enabled, the RAW_TRANSFER should be enabled before the buffer is destroyed.

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have compiled all hdl projects and libraries affected by this PR
  • I have tested in hardware affected projects, at least on relevant boards
  • I have commented my code, at least hard-to-understand parts
  • I have signed off all commits from this PR
  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Critical Warnings on compilation
  • I have added new hdl testbenches or updated existing ones

@AndreiGrozav AndreiGrozav force-pushed the m2k_dac_last_sample_hold_default branch from 2feba8f to 7d851d7 Compare October 10, 2023 11:12
@AndreiGrozav AndreiGrozav force-pushed the m2k_dac_last_sample_hold_default branch 2 times, most recently from 4583fc2 to 3a22540 Compare October 26, 2023 06:38
@AndreiGrozav AndreiGrozav marked this pull request as ready for review October 26, 2023 11:48
@AndreiGrozav AndreiGrozav removed the request for review from dbogdan October 26, 2023 12:27
@AndreiGrozav AndreiGrozav force-pushed the m2k_dac_last_sample_hold_default branch from 3a22540 to 88c9757 Compare November 9, 2023 07:46
@AndreiGrozav
m2k: Remove dac last_sample_hold control
74f82be 
axi_dac_interpolate - Remove last sample hold control
axi_ad9963 - Remove last sample hold control and set as default the
last sample hold functionality plus code optimization changes.
@AndreiGrozav AndreiGrozav force-pushed the m2k_dac_last_sample_hold_default branch from 88c9757 to 17fb458 Compare November 9, 2023 13:12
@AndreiGrozav
axi_dac_interpolate: Improve the ctrl logic
e2da33b 
1. Simplify the control logic by adding a state machine.
The improvements are on code readability and reliability.

2.Add a flush feature which can be used to clean the data from the DMA fifo.
This is useful when the DMA is programmed in cyclic mode and
data transmission is stopped by dma_transfer_suspend flag
The software intervention is reduced at setting the flag(dma_flush_en).
Flushing can also be done when activating the raw value with dma_flush_en active.

3. Add raw value support. Through this changes a user can set
the dac output to a fixed predefined value in the following two cases:
  1. direct, without using the dma.
  2. with dma, as a hold value. The fixed value will be kipped after a cyclic
buffer is stopped by axi_dac_interpolate, through dma_transfer_suspend
register/signal.
The raw value ca be set and transmitted independently on each channel.
The predefined value is stored in reg 0x19(0x64). For more details se
the documentation available at
https://wiki.analog.com/resources/fpga/docs/axi_dac_interpolate
@AndreiGrozav AndreiGrozav force-pushed the m2k_dac_last_sample_hold_default branch from 17fb458 to e2da33b Compare November 14, 2023 11:45
@AndreiGrozav AndreiGrozav merged commit 39b2a2b into main Dec 12, 2023
1 check failed
@AndreiGrozav AndreiGrozav deleted the m2k_dac_last_sample_hold_default branch December 12, 2023 14:51
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@IuliaCMoldovan IuliaCMoldovan IuliaCMoldovan approved these changes

@acostina acostina acostina approved these changes

@PopPaul2021 PopPaul2021 Awaiting requested review from PopPaul2021 PopPaul2021 is a code owner

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@AndreiGrozav @acostina @IuliaCMoldovan