update python tests for sreg

anikau31 · Dec 10, 2019 · 1e8d362 · 1e8d362
1 parent f591420
commit 1e8d362
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Showing 3 changed files with 22 additions and 14 deletions.
diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt
@@ -45,7 +45,7 @@ endforeach()
 # for pytest tests
 if(PY_TESTS_ON)
   add_test(NAME python-tests
-    COMMAND ${PYTHON_EXECUTABLE} -m pytest ${CMAKE_CURRENT_SOURCE_DIR}
+    COMMAND ${PYTHON_EXECUTABLE} -m pytest --color=yes ${CMAKE_CURRENT_SOURCE_DIR}
     WORKING_DIRECTORY ${PROJECT_SOURCE_DIR} )
 endif()
 
diff --git a/tests/verilog-conversion/llnl.py b/tests/verilog-conversion/llnl.py
@@ -55,10 +55,13 @@ def do_diff(golden, generated):
     print(''.join(diff))
     return len(diff) == 0
 
-def run_sexp_matched_test(module_name):
+def run_sexp_matched_test(module_name, args=None):
     parser = get_parser()
-    args = parser.parse_args()
-    keep_sexp = args.keep_sexp
+    if args is None:
+        keep_sexp = parser.get_default('keep_sexp')
+    else:
+        args_ = parser.parse_args()
+        keep_sexp = args_.keep_sexp
     golden_standard_file = _golden_sexp_file.format(module_name)
     with open(golden_standard_file, 'r') as f:
         golden = f.read()
@@ -76,11 +79,15 @@ def run_sexp_matched_test(module_name):
         if not keep_sexp:
             subprocess.run('rm -rf ./{}_hdl.txt'.format(module_name), shell=True)
 
-def run_verilog_matched_test(module_name):
+def run_verilog_matched_test(module_name, args=None):
     parser = get_parser()
-    args = parser.parse_args()
-    keep_sexp = args.keep_sexp
-    keep_v = args.keep_v
+    if args is None:
+        keep_sexp = parser.get_default('keep_sexp')
+        keep_v = parser.get_default('keep_v')
+    else:
+        args_ = parser.parse_args()
+        keep_sexp = args_.keep_sexp
+        keep_v = args_.keep_v
     golden_standard_file = _golden_verilog_file.format(module_name)
     with open(golden_standard_file, 'r') as f:
         golden = f.read()

diff --git a/tests/verilog-conversion/test_sreg.py b/tests/verilog-conversion/test_sreg.py
@@ -1,12 +1,13 @@
 import os
+import sys
 from llnl import run_verilog_matched_test, run_sexp_matched_test
 
-def test_sreg_sexp():
-    assert run_sexp_matched_test('sreg'), "sreg sexp should match golden standard"
+def test_sreg_sexp(args=None):
+    assert run_sexp_matched_test('sreg', args), "sreg sexp should match golden standard"
 
-def test_sreg_verilog():
-    assert run_verilog_matched_test('sreg'), "sreg verilog should match golden standard"
+def test_sreg_verilog(args=None):
+    assert run_verilog_matched_test('sreg', args), "sreg verilog should match golden standard"
 
 if __name__ == '__main__':
-    test_sreg_verilog()
-    test_sreg_sexp()
+    test_sreg_verilog(args)
+    test_sreg_sexp(args)