checkpoint: wm8731 loopback

antoinevg · Oct 12, 2022 · 1a6926d · 1a6926d
1 parent aa9ae4e
commit 1a6926d
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Showing 3 changed files with 16 additions and 49 deletions.
diff --git a/examples/audio_wm8731.rs b/examples/audio_wm8731.rs
@@ -57,9 +57,8 @@ fn main() -> ! {
                 break;
             }
         }
-        //println!("{:02x}", register);
         unsafe {
-            riscv::asm::delay(50_000_000);
+            riscv::asm::delay(5_000_000);
         }
     }
 
@@ -128,7 +127,7 @@ unsafe fn handle_dma_interrupt(half: bool, is_tx: bool) {
     }
 
     // fill tx_buffer
-    let mut frame_index = 0;
+    /*let mut frame_index = 0;
     while frame_index < half_buffer_length {
         // whoop! whoop!
         //F1 += 0.01;
@@ -141,9 +140,9 @@ unsafe fn handle_dma_interrupt(half: bool, is_tx: bool) {
         let right = dsp::f32_to_u24(OSC2.step());
         let tx = frame_index + skip.0;
         TX_BUFFER[tx + 0] = left as u32;
-        //TX_BUFFER[tx + 1] = right as u32;
+        TX_BUFFER[tx + 1] = right as u32;
         frame_index += 2;
-    }
+    }*/
 
     // debug
     static mut COUNTER: usize = 0;

diff --git a/examples/device/wm8731.rs b/examples/device/wm8731.rs
@@ -20,47 +20,14 @@ pub enum Register {
     RESET  = 0x0F,
 }
 
-/*pub const DEFAULT_CONFIG: &[(Register, u16)] = &[
-    // power-on codec
-    (Register::PWR,    0b0000_0000),
-
-    // configure analog routing
-    //(Register::APANA,  0b0001_0010),   // select line for adc input, dac select, mute mic
-    (Register::APANA,  0b0001_0101),   // select mic for adc input, mic boost
-
-    // configure digital routing
-    //(Register::APDIGI, 0b0_0000),        // default
-    (Register::APDIGI, 0b1_0110),        // store dc-offset, de-emphasis for fs=48kHz, enable hpf
-
-    // configure interface format
-    //(Register::IFACE,  0b0100_1110),     // i2s_clock_internal, 32bit, i2s
-    (Register::IFACE,  0b0100_1010),     // i2s_clock_internal, 24bit, i2s
-    //(Register::IFACE,  0b0100_0010),     // i2s_clock_internal, 16bit, i2s
-
-    // configure mode and sample-rate
-    (Register::SRATE,  0b00_0000),       // mode=0, fs=48kHz
-
-    // switch codec to active
-    (Register::ACTIVE, 0b1),
-
-    // set input level
-    (Register::LINVOL, 0b0_0001_0111),   // 0dB
-    (Register::RINVOL, 0b0_0001_0111),   // 0dB
-
-    // set output level
-    (Register::LHPOUT, 0b0_1111_1001),   // 0dB
-    (Register::RHPOUT, 0b0_1111_1001),   // 0dB
-];*/
-
-
 pub const DEFAULT_CONFIG: &[(Register, u16)] = &[
     // power-on codec
     (Register::PWR,    0b0000_0000),
 
     // reset codec
     (Register::RESET,  0x0),
 
-    // switch to inactive
+    // switch codec to inactive
     (Register::ACTIVE, 0b0),
 
     // configure power
@@ -75,8 +42,8 @@ pub const DEFAULT_CONFIG: &[(Register, u16)] = &[
     (Register::APDIGI, 0b0_0000),        // default
 
     // configure interface format
-    (Register::IFACE,  0b0100_1110),     // i2s_clock_internal, 32bit, i2s
-    //(Register::IFACE,  0b0100_1010),     // i2s_clock_internal, 24bit, i2s
+    //(Register::IFACE,  0b0100_1110),     // i2s_clock_internal, 32bit, i2s
+    (Register::IFACE,  0b0100_1010),     // i2s_clock_internal, 24bit, i2s
     //(Register::IFACE,  0b0100_0010),     // i2s_clock_internal, 16bit, i2s
 
     // configure mode and sample-rate
@@ -90,6 +57,9 @@ pub const DEFAULT_CONFIG: &[(Register, u16)] = &[
     (Register::LHPOUT, 0b0_1111_1001),   // 0dB
     (Register::RHPOUT, 0b0_1111_1001),   // 0dB
 
+    // switch codec to inactive
+    (Register::ACTIVE, 0b0),
+
     // switch codec to active
     (Register::ACTIVE, 0b1),
 

diff --git a/src/i2s.rs b/src/i2s.rs
@@ -157,8 +157,8 @@ fn configure_i2s_pcm2(i2s_pcm2: &I2S_PCM2) {
     // configure i2c_pcm2 mode: external clock, i2s mode
     i2s_pcm2.i2s_pcm_ctl.modify(|_, w| {
         w
-            .rx_sync_en().disable()       // rx_sync: enable
-            .rx_sync_en_start().disable() // only takes effect if rx_sync_en is high
+            .rx_sync_en().enable()       // rx_sync: enable
+            .rx_sync_en_start().enable() // only takes effect if rx_sync_en is high
             .bclk_out().input()          // i2s_clock_external
             .lrck_out().input()          // i2s_clock_external
             .dout0_en().enable()
@@ -177,9 +177,9 @@ fn configure_i2s_pcm2(i2s_pcm2: &I2S_PCM2) {
     i2s_pcm2.i2s_pcm_fmt0.modify(|_, w| unsafe {
         w
             .lrck_polarity().high()       // low: left, high: right - I2S_CHANNEL_FMT_RIGHT_LEFT ??? check codec iface register
-            .lrck_period().bits(31)       // period = sr - 1
-            .sr().bits_24()               // sample resolution: 32 bit
-            .sw().bits_32()               // slot width: 32 bit
+            .lrck_period().bits(31)       // period = width - 1
+            .sr().bits_24()               // sample resolution: 24 bit
+            .sw().bits_24()               // slot width: 24 bit
             .blck_polarity().normal()     // normal: negative, invert: positive
             .edge_transfer().alternate()  // in conjunction with blck_polarity sets pos/neg edge ???
 
@@ -193,9 +193,7 @@ fn configure_i2s_pcm2(i2s_pcm2: &I2S_PCM2) {
             .tx_pdm().linear() // linear PCM / u-law / A-law
     });
     i2s_pcm2.i2s_pcm_chcfg.modify(|_, w| unsafe {
-        w.tx_slot_hiz().normal()  // defaults - only used for TDM
-         .tx_state().zero()       // defaults - only used for TDM
-         .tx_slot_num().bits(1)   // DMA/FIFO num slots = n + 1
+        w.tx_slot_num().bits(1)   // DMA/FIFO num slots = n + 1
          .rx_slot_num().bits(1)
     });
     i2s_pcm2.i2s_pcm_tx0chsel.modify(|_, w| unsafe {