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checkpoint: i2s, dma and drq configuration
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@antoinevg
antoinevg committed Oct 6, 2022
1 parent df4259f commit 97323cc
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Showing 6 changed files with 226 additions and 73 deletions.
4 changes: 2 additions & 2 deletions Cargo.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -9,8 +9,8 @@ edition = "2021"
riscv = { git = "https://github.com/rust-embedded/riscv" }
riscv-rt = { git = "https://github.com/rust-embedded/riscv-rt" }
#d1-pac = { git = "https://github.com/duskmoon314/aw-pac" }
d1-pac = { git = "https://github.com/antoinevg/aw-pac", branch = "antoinevg/i2s" }
#d1-pac = { path = "../upstream/aw-pac.git/d1-pac" }
#d1-pac = { git = "https://github.com/antoinevg/aw-pac", branch = "antoinevg/i2s" }
d1-pac = { path = "../upstream/aw-pac.git/d1-pac" }
panic-halt = "=0.2.0"

[profile.release]
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78 changes: 27 additions & 51 deletions examples/audio_wm8731.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -11,8 +11,8 @@ use d1_pac as pac;
use panic_halt as _;

use hello_d1::twi;
//use hello_d1::i2s;
//use hello_d1::dmac;
use hello_d1::i2s;
use hello_d1::dmac;
use hello_d1::logging;
use hello_d1::plic;
use hello_d1::println;
Expand All @@ -34,7 +34,7 @@ fn main() -> ! {
gpio.pc_cfg0.write(|w| w.pc1_select().output());

// ccu
let ccu = p.CCU;
let mut ccu = p.CCU;

// configure wm8731 over i2c
println!("configure wm8731");
Expand All @@ -61,32 +61,29 @@ fn main() -> ! {
}
}

/*
// i2s
let mut i2s = i2s::I2s::new(p.I2S_PCM2, &mut ccu);
let mut i2s = i2s::I2s::new(p.I2S_PCM2, &gpio, &ccu);

// dmac
let mut dmac = dmac::Dmac::new(p.DMAC, &mut ccu);
*/

// plic
/*let plic = plic::Plic::new(p.PLIC);
let plic = plic::Plic::new(p.PLIC);
unsafe {
//plic.set_priority(pac::Interrupt::TWI0, plic::Priority::P1);
//plic.set_priority(pac::Interrupt::DMAC_NS, plic::Priority::P1);
//plic.set_priority(pac::Interrupt::I2S_PCM2, plic::Priority::P1);
//plic.unmask(pac::Interrupt::TWI0);
//plic.unmask(pac::Interrupt::DMAC_NS);
//plic.unmask(pac::Interrupt::I2S_PCM2);
}*/
plic.set_priority(pac::Interrupt::DMAC_NS, plic::Priority::P1);
plic.set_priority(pac::Interrupt::I2S_PCM2, plic::Priority::P1);
plic.unmask(pac::Interrupt::DMAC_NS);
plic.unmask(pac::Interrupt::I2S_PCM2);
}

// enable interrupts
/*unsafe {
unsafe {
riscv::interrupt::enable();
riscv::register::mie::set_mext();
}*/
}

// i2s - start
//i2s.start(&mut dmac, unsafe { &TX_BUFFER });
i2s.start(&mut dmac, unsafe { &TX_BUFFER });

// blinky
loop {
Expand Down Expand Up @@ -126,7 +123,7 @@ unsafe fn handle_dma_interrupt(half: bool) {
F = 0.;
}
OSC.dx = (1. / 48_000.) * (220. + F);
let sample = dsp::f32_to_u20(OSC.step());
let sample = dsp::f32_to_u32(OSC.step());

let x = frame_index + skip;
TX_BUFFER[x + 0] = sample as u32;
Expand All @@ -144,32 +141,6 @@ extern "C" fn MachineExternal() {
let claim = plic.claim();

match claim {
pac::Interrupt::TWI0 => {
let twi0 = unsafe { &*pac::TWI0::PTR };

//println!("TIW0");

/*if twi0.twi_cntr.read().int_flag().bit_is_set() {
twi0.twi_cntr.modify(|_, w| {
w.int_flag().clear_bit()
});
while twi0.twi_cntr.read().int_flag().bit_is_set() {
println!(".");
}
}*/

/*twi0.twi_cntr.modify(|_, w| {
w.int_flag().clear_bit()
});*/

/*while twi0.twi_cntr.read().int_flag().bit_is_set() {
println!("..");
}*/

//let status = twi0.twi_stat.read().sta();
//println!("TWI0: {} {:?}", status.bits(), status.variant().unwrap());
//println!("TWI0: {:0x}", status.bits());
}
pac::Interrupt::DMAC_NS => {
let dmac = unsafe { &*pac::DMAC::PTR };

Expand All @@ -192,21 +163,26 @@ extern "C" fn MachineExternal() {
}
pac::Interrupt::I2S_PCM2 => {
let i2s = unsafe { &*pac::I2S_PCM2::PTR };
/*

// get pending interrupts
let pending = i2s.ac_dac_fifos.read();
let pending = i2s.i2s_pcm_ista.read();

// clear all pending interrupts
if pending.txe_int().is_pending() { // TODO don't need this
println!("empty");
i2s.i2s_pcm_ista.write(|w| w.txe_int().set_bit());
while i2s.i2s_pcm_ista.read().txe_int().bit_is_set() {}
}
if pending.txo_int().is_pending() {
println!("overrun");
i2s.ac_dac_fifos.write(|w| w.txo_int().set_bit());
while i2s.ac_dac_fifos.read().txo_int().bit_is_set() {}
i2s.i2s_pcm_ista.write(|w| w.txo_int().set_bit());
while i2s.i2s_pcm_ista.read().txo_int().bit_is_set() {}
}
if pending.txu_int().is_pending() {
println!("underrun");
i2s.ac_dac_fifos.write(|w| w.txu_int().set_bit());
while i2s.ac_dac_fifos.read().txu_int().bit_is_set() {}
}*/
i2s.i2s_pcm_ista.write(|w| w.txu_int().set_bit());
while i2s.i2s_pcm_ista.read().txu_int().bit_is_set() {}
}
}
x => {
println!("Unexpected claim: {:?}", x);
Expand Down
45 changes: 39 additions & 6 deletions examples/device/wm8731.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -9,8 +9,8 @@ pub const DEVICE_ID_B: u8 = 0x1b;
pub enum Register {
LINVOL = 0x00,
RINVOL = 0x01,
LOUT1V = 0x02,
ROUT1V = 0x03,
LHPOUT = 0x02,
RHPOUT = 0x03,
APANA = 0x04,
APDIGI = 0x05, // 0000_0101
PWR = 0x06,
Expand All @@ -19,7 +19,7 @@ pub enum Register {
ACTIVE = 0x09, // 0000_1001
RESET = 0x0F,
}

/*
pub const DEFAULT_CONFIG: &[(Register, u16)] = &[
(Register::PWR, 0x80),
(Register::RESET, 0x00),
Expand All @@ -31,7 +31,8 @@ pub const DEFAULT_CONFIG: &[(Register, u16)] = &[
(Register::APDIGI, 0x00),
(Register::PWR, 0x00),
(Register::IFACE, 0x02),
(Register::IFACE, 0b01001110), // MS=master, IWL=32bit, FORMAT=i2s
//(Register::IFACE, 0b00001110), // MS=slave, IWL=32bit, FORMAT=i2s
//(Register::IFACE, 0b0000_0010), // 0x02 FORMAT=b10 IRL=b00 LRP=0 LRSWAP=0 MS=0 BCKLINV=0
//(Register::IFACE, 0b0100_0010), // 0x42 FORMAT=b10 IRL=b00 LRP=0 LRSWAP=0 MS=1 BCKLINV=0
Expand All @@ -40,7 +41,39 @@ pub const DEFAULT_CONFIG: &[(Register, u16)] = &[
(Register::LINVOL, 0x17),
(Register::RINVOL, 0x17),
(Register::LOUT1V, 0x79), // 0dB
(Register::ROUT1V, 0x79), // 0dB
(Register::LHPOUT, 0x79), // 0dB
(Register::RHPOUT, 0x79), // 0dB
(Register::ACTIVE, 0x01),
];
*/

pub const DEFAULT_CONFIG: &[(Register, u16)] = &[
// reset Codec
(Register::RESET, 0x00),

// set line inputs 0dB - TODO dev board only has mic in, these are NC
(Register::LINVOL, 0x17),
(Register::RINVOL, 0x17),

// set headphone out to 0dB
(Register::LHPOUT, 0b0_0111_1001),
(Register::RHPOUT, 0b0_0111_1001),

// set analog and digital routing
(Register::APANA, 0b0_0001_0100), // select mic for adc input, dac select
(Register::APDIGI, 0b0_0000_0001), // disable hpf

// configure power management
//(Register::PWR, 0b0_0100_0000), // clkout power down
(Register::PWR, 0b0_0000_0000), // master, so don't power down clock

// configure digital format
(Register::IFACE, 0b0_0100_1110), // MS=master, IWL=32bit, FORMAT=i2s
//(Register::IFACE, 0b0_0000_1110), // MS=slave, IWL=32bit, FORMAT=i2s

// set samplerate
(Register::SRATE, 0x00), // fs=48kHz

(Register::ACTIVE, 0x00),
(Register::ACTIVE, 0x01),
];
13 changes: 13 additions & 0 deletions examples/dsp/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -26,3 +26,16 @@ pub fn f32_to_u20(x: f32) -> u32 {
};
(x as i32) as u32
}

#[inline(always)]
pub fn f32_to_u32(x: f32) -> u32 {
let x = x * 2_147_483_647.;
let x = if x > 2_147_483_647. {
2_147_483_647.
} else if x < -2_147_483_648. {
-2_147_483_648.
} else {
x
};
(x as i32) as u32
}
6 changes: 0 additions & 6 deletions src/dmac.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -25,12 +25,6 @@ pub struct Dmac {
impl Dmac {
pub fn new(dmac: DMAC, ccu: &mut CCU) -> Self {
ccu.dma_bgr.write(|w| w.gating().pass().rst().deassert());
// disable auto-gating, probably not needed?
/*dmac.dmac_auto_gate.write(
|w| w.dma_chan_circuit().set_bit()
.dma_common_circuit().set_bit()
.dma_mclk_circuit().set_bit()
);*/
Self {
dmac,
channels: [
Expand Down
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