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Additional Instruction Memories for NibbleBuddy
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These ROM modules contain the binary versions of the additional NibbleBuddy Assembly programs written and in the Assembly directory of the repository, as produced by the Python assembler in the same directory.
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aofarmakis authored Dec 7, 2024
1 parent b5ef5b6 commit da8039b
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34 changes: 34 additions & 0 deletions Verilog/instruction_memory_byte_addition.v
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module instruction_memory_fibonacci (address, data);

input [4:0] address;
output reg [7:0] data;

always @(address) begin
case(address)
00: data = 8'b00110101;
01: data = 8'b00000000;
02: data = 8'b00110100;
03: data = 8'b00000001;
04: data = 8'b00110001;
05: data = 8'b00000010;
06: data = 8'b00111111;
07: data = 8'b00000011;
08: data = 8'b1000xxxx;
09: data = 8'b00100000;
10: data = 8'b01000001;
11: data = 8'b00000100;
12: data = 8'b00100010;
13: data = 8'b01000011;
14: data = 8'b00000101;
15: data = 8'b00110000;
16: data = 8'b01010000;
17: data = 8'b00000110;
18: data = 8'b00100100;
19: data = 8'b00100101;
20: data = 8'b00100110;
21: data = 8'b0001xxxx;
default: data = 8'b00;
endcase
end

endmodule
29 changes: 29 additions & 0 deletions Verilog/instruction_memory_circular_shift_left.v
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module instruction_memory_fibonacci (address, data);

input [4:0] address;
output reg [7:0] data;

always @(address) begin
case(address)
00: data = 8'b00111001;
01: data = 8'b00000000;
02: data = 8'b00110010;
03: data = 8'b00000001;
04: data = 8'b10100110;
05: data = 8'b11101111;
06: data = 8'b1000xxxx;
07: data = 8'b00100000;
08: data = 8'b01000000;
09: data = 8'b01010000;
10: data = 8'b00000000;
11: data = 8'b00100001;
12: data = 8'b01011111;
13: data = 8'b00000001;
14: data = 8'b10100110;
15: data = 8'b00100000;
16: data = 8'b0001xxxx;
default: data = 8'b00;
endcase
end

endmodule
26 changes: 26 additions & 0 deletions Verilog/instruction_memory_infinite_counting.v
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module instruction_memory_fibonacci (address, data);

input [4:0] address;
output reg [7:0] data;

always @(address) begin
case(address)
00: data = 8'b00110000;
01: data = 8'b00000000;
02: data = 8'b00000001;
03: data = 8'b00100001;
04: data = 8'b01010001;
05: data = 8'b01000000;
06: data = 8'b00000001;
07: data = 8'b1000xxxx;
08: data = 8'b10100011;
09: data = 8'b00100000;
10: data = 8'b01010001;
11: data = 8'b1000xxxx;
12: data = 8'b00000000;
13: data = 8'b11100011;
default: data = 8'b00;
endcase
end

endmodule
29 changes: 29 additions & 0 deletions Verilog/instruction_memory_logical_shift_left.v
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module instruction_memory_fibonacci (address, data);

input [4:0] address;
output reg [7:0] data;

always @(address) begin
case(address)
00: data = 8'b00111001;
01: data = 8'b00000000;
02: data = 8'b00110010;
03: data = 8'b00000001;
04: data = 8'b10100110;
05: data = 8'b11101111;
06: data = 8'b1000xxxx;
07: data = 8'b00100000;
08: data = 8'b01000000;
09: data = 8'b1000xxxx;
10: data = 8'b00000000;
11: data = 8'b00100001;
12: data = 8'b01011111;
13: data = 8'b00000001;
14: data = 8'b10100110;
15: data = 8'b00100000;
16: data = 8'b0001xxxx;
default: data = 8'b00;
endcase
end

endmodule
42 changes: 42 additions & 0 deletions Verilog/instruction_memory_one-hot_detector.v
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module instruction_memory_fibonacci (address, data);

input [4:0] address;
output reg [7:0] data;

always @(address) begin
case(address)
00: data = 8'b00111100;
01: data = 8'b00000000;
02: data = 8'b00111000;
03: data = 8'b00000001;
04: data = 8'b00110000;
05: data = 8'b00000010;
06: data = 8'b00100001;
07: data = 8'b01110000;
08: data = 8'b01010001;
09: data = 8'b11001011;
10: data = 8'b11111001;
11: data = 8'b00100001;
12: data = 8'b01000001;
13: data = 8'b00000001;
14: data = 8'b00100010;
15: data = 8'b01010000;
16: data = 8'b00000010;
17: data = 8'b01011110;
18: data = 8'b11010100;
19: data = 8'b11111001;
20: data = 8'b00100000;
21: data = 8'b01010001;
22: data = 8'b00000000;
23: data = 8'b11001011;
24: data = 8'b11111100;
25: data = 8'b00110000;
26: data = 8'b00000010;
27: data = 8'b11111100;
28: data = 8'b00100010;
29: data = 8'b0001xxxx;
default: data = 8'b00;
endcase
end

endmodule
44 changes: 44 additions & 0 deletions Verilog/instruction_memory_unsigned_multiplication.v
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module instruction_memory_fibonacci (address, data);

input [4:0] address;
output reg [7:0] data;

always @(address) begin
case(address)
00: data = 8'b00111100;
01: data = 8'b00000000;
02: data = 8'b00111000;
03: data = 8'b00000001;
04: data = 8'b00100000;
05: data = 8'b00000010;
06: data = 8'b01110000;
07: data = 8'b01000010;
08: data = 8'b11001101;
09: data = 8'b00100001;
10: data = 8'b00000000;
11: data = 8'b00100010;
12: data = 8'b00000001;
13: data = 8'b00110000;
14: data = 8'b00000010;
15: data = 8'b00100001;
16: data = 8'b10110010;
17: data = 8'b11111101;
18: data = 8'b1000xxxx;
19: data = 8'b00100010;
20: data = 8'b01000000;
21: data = 8'b00000010;
22: data = 8'b00100011;
23: data = 8'b01010000;
24: data = 8'b00000011;
25: data = 8'b00100001;
26: data = 8'b01011111;
27: data = 8'b00000001;
28: data = 8'b10110010;
29: data = 8'b00100010;
30: data = 8'b00100011;
31: data = 8'b0001xxxx;
default: data = 8'b00;
endcase
end

endmodule
29 changes: 29 additions & 0 deletions Verilog/instruction_memory_xor_xnor.v
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module instruction_memory_fibonacci (address, data);

input [4:0] address;
output reg [7:0] data;

always @(address) begin
case(address)
00: data = 8'b00110101;
01: data = 8'b00000000;
02: data = 8'b00110011;
03: data = 8'b00000001;
04: data = 8'b01100000;
05: data = 8'b00000010;
06: data = 8'b01100000;
07: data = 8'b00000011;
08: data = 8'b00100010;
09: data = 8'b01100001;
10: data = 8'b01100011;
11: data = 8'b00000010;
12: data = 8'b01100010;
13: data = 8'b00000011;
14: data = 8'b00100010;
15: data = 8'b00100011;
16: data = 8'b0001xxxx;
default: data = 8'b00;
endcase
end

endmodule

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