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GH-43687: [C++] Compute: fix register kernel SimdLevel for AddMinMax512AggKernels #43704
GH-43687: [C++] Compute: fix register kernel SimdLevel for AddMinMax512AggKernels #43704
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+1
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I'm approving and we should merge this, but I'm working on a PR that removes the SimdLevel template parameter alltogether as there is no need to runtime dispatch different SIMD levels when we are relying on compiler auto-vectorization.
Discussion here: #7871
Will merge this firstly |
Supported benchmark command examples:
To run all benchmarks: To filter benchmarks by language: To filter Python and R benchmarks by name: To filter C++ benchmarks by archery --suite-filter and --benchmark-filter: For other |
@ursabot please benchmark command=cpp-micro --suite-filter=arrow-acero-aggregate-benchmark --benchmark-filter=MinMaxKernel* --iterations=3 |
Benchmark runs are scheduled for commit cb073ed. Watch https://buildkite.com/apache-arrow and https://conbench.ursa.dev for updates. A comment will be posted here when the runs are complete. |
Thanks for your patience. Conbench analyzed the 0 benchmarking runs that have been run so far on PR commit cb073ed. None of the specified runs were found on the Conbench server. The full Conbench report has more details. |
After merging your PR, Conbench analyzed the 7 benchmarking runs that have been run so far on merge-commit 2e434da. There were 3 benchmark results indicating a performance regression:
The full Conbench report has more details. It also includes information about 5 possible false positives for unstable benchmarks that are known to sometimes produce them. |
Rationale for this change
See #43687
What changes are included in this PR?
Change Registered AVX2 to AVX512
Are these changes tested?
No
Are there any user-facing changes?
maybe bugfix