add message; fix layout rewrite mismatch

apache · Jan 23, 2021 · 0d6c891 · 0d6c891
1 parent ec7ae58
commit 0d6c891
Show file tree

Hide file tree

Showing 3 changed files with 6 additions and 3 deletions.
diff --git a/python/tvm/auto_scheduler/dispatcher.py b/python/tvm/auto_scheduler/dispatcher.py
@@ -261,7 +261,9 @@ def query(self, target, workload_key, has_complex_op, dag):
                 "-----------------------------------\n"
                 "Cannot find tuned schedules for target=%s, workload_key=%s. "
                 "A fallback TOPI schedule is used, "
-                "which may bring great performance regression or even compilation failure. "
+                "which may hurt performance or fail to compile. "
+                "If you've tuned this workload before, you may need to update workload_key "
+                "using the script in https://github.com/apache/tvm/pull/7317. "
                 "Compute DAG info:\n%s" % (target, workload_key, dag)
             )
             if msg not in self.messages:

diff --git a/python/tvm/auto_scheduler/relay_integration.py b/python/tvm/auto_scheduler/relay_integration.py
@@ -309,7 +309,8 @@ def auto_schedule_topi(outs):
                 return None
 
             # rewrite the layout and update the context for the new dag
-            dag = ComputeDAG(outs)
+            io_tensors, _, _ = traverse_to_get_io_tensors(outs)
+            dag = ComputeDAG(io_tensors)
             new_dag = dag.rewrite_layout_from_state(state)
             new_key = new_dag.workload_key()
             if new_key != key:

diff --git a/tutorials/auto_scheduler/ci_logs/resnet-50-NHWC-B1-llvm.json b/tutorials/auto_scheduler/ci_logs/resnet-50-NHWC-B1-llvm.json
@@ -1,4 +1,4 @@
-# Provide valid schedules for resnet-50 for CPU.
+# Provide valid schedules for resnet-50 for CPU.    
 # This is used to run the tutorial on the documentation web server.
 {"i": [["[\"d7b65649a4dd54becea0a52aabbc5af5\", 1, 1000, 1, 1000]", "llvm -keys=cpu -link-params=0 -mcpu=core-avx2", [8, 64, 64, 0, 0, 0, 0, 0], "", 2], [[], [["SP", 3, 1, 1000, [50], 1], ["RF", 3, 2, 1], ["RE", 3, [0, 2, 1]], ["SP", 1, 1, 1000, [20], 1], ["RF", 1, 2, 1], ["RE", 1, [0, 2, 1]], ["CR", 6], ["CA", 5, 6, 1], ["CR", 4], ["CA", 2, 3, 1], ["AN", 1, 0, 3], ["FU", 3, [0, 1]], ["AN", 3, 0, 3], ["AN", 4, 0, 3], ["FU", 6, [0, 1]], ["AN", 6, 0, 3], ["PR", 1, 0, "auto_unroll_max_step$16"], ["PR", 2, 0, "auto_unroll_max_step$16"], ["PR", 4, 0, "auto_unroll_max_step$16"], ["PR", 5, 0, "auto_unroll_max_step$64"]]]], "r": [[8.75e-06, 1.0781e-05, 9.875e-06, 9.836e-06, 1.0357e-05, 1.0238e-05, 1.0341e-05, 9.75e-06, 9.561e-06, 1.0122e-05], 0, 0.17921, 1606960872], "v": "v0.5"}
 {"i": [["[\"69115f188984ae34ede37c3b8ca40b43\", 1, 7, 7, 2048, 1, 1, 1, 2048]", "llvm -keys=cpu -link-params=0 -mcpu=core-avx2", [8, 64, 64, 0, 0, 0, 0, 0], "", 2], [[], [["CA", 1, 2, 3], ["FU", 2, [0, 1, 2, 3]], ["AN", 2, 0, 3], ["PR", 1, 0, "auto_unroll_max_step$16"]]]], "r": [[6.28e-06, 8.176e-06, 8.048e-06, 7.942e-06, 7.977e-06, 8.002e-06, 8.093e-06, 7.924e-06, 7.943e-06, 7.924e-06], 0, 0.130759, 1606960900], "v": "v0.5"}