cortex r5 added

apps/microtvm/zephyr/host_driven/boards/qemu_cortex_r5.conf

@@ -0,0 +1,29 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements.  See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership.  The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied.  See the License for the
+# specific language governing permissions and limitations
+# under the License.
+
+# This file is specific to the QEMU-emulated Cortex R5 microTVM board.
+
+# For TVMPlatformGenerateRandom(). Remember, these values do not need to be truly random.
+CONFIG_TEST_RANDOM_GENERATOR=y
+CONFIG_TIMER_RANDOM_GENERATOR=y
+
+# Default stack size is 1k, this is required for debug mode. 
+CONFIG_MAIN_STACK_SIZE=4000
+
+
+# For models with floating point.
+CONFIG_FPU=y

apps/microtvm/zephyr/qemu-hack/qemu-system-arm

@@ -1 +1 @@
-./qemu-system-i386
+qemu-system-i386

apps/microtvm/zephyr/qemu-hack/qemu-system-xilinx-aarch64

@@ -0,0 +1 @@
+qemu-system-i386

python/tvm/target/target.py

@@ -278,9 +278,9 @@ def intel_graphics(model="unknown", options=None):
     opts = _merge_opts(opts, options)
     return Target(" ".join(["opencl"] + opts))
 
-
 MICRO_SUPPORTED_MODELS = {
     "host": [],
+    "zynq_mp_r5": ["-mcpu=cortex-r5"],
     "mps2_an521": ["-mcpu=cortex-m33"],
     "nrf5340dk": ["-mcpu=cortex-m33"],
     "stm32f746xx": ["-mcpu=cortex-m7", "-march=armv7e-m"],

tests/micro/zephyr/conftest.py

@@ -29,6 +29,7 @@
     "stm32f746xx_disco": ("stm32f746xx", "stm32f746g_disco"),
     "stm32f746xx_nucleo": ("stm32f746xx", "nucleo_f746zg"),
     "stm32l4r5zi_nucleo": ("stm32l4r5zi", "nucleo_l4r5zi"),
+    "zynq_mp_r5": ("zynq_mp_r5", "qemu_cortex_r5"),
 }