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[Topi][Hexagon] Implement Cast F32ToF16 and F16ToF32 Slice Op #11561
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190e4d9
[Topi][Hexagon] Implement Cast F32ToF16 and F16ToF32 Slice Op
arangasa 1b06dfb
Merge branch 'main' into slice_op_cast
7b8b1d2
Fix linter issues. Move test to topi directory.
7d710e5
run through black.
6b90428
Merge branch 'main' into slice_op_cast
arangasa c7eb162
Fix pylint error
a65ee3b
Merge branch 'main' into slice_op_cast
arangasa 5e98f1b
Use tvm.testing.main
arangasa 92b033a
Merge branch 'main' into slice_op_cast
arangasa 229d38f
Merge branch 'main' into slice_op_cast
arangasa f531e00
Reuse functions
arangasa 7278113
Merge branch 'main' into slice_op_cast
arangasa 258828c
Fix tvm.testing.main invocation
arangasa e4d8525
Merge branch 'main' into slice_op_cast
arangasa 2f38248
Merge branch 'main' into slice_op_cast
arangasa 2a3fb2a
Fix lint issues; Address review comments
arangasa f4f6d5b
Merge branch 'main' into slice_op_cast
arangasa 7a82e87
run through black.
arangasa 7fd18aa
Merge branch 'main' into slice_op_cast
arangasa 1196853
Disable tests on hardware.
arangasa 6c8392a
Fix test failure
arangasa 264fe76
Merge branch 'main' into slice_op_cast
arangasa 5bddaef
Merge branch 'main' into slice_op_cast
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# Licensed to the Apache Software Foundation (ASF) under one | ||
# or more contributor license agreements. See the NOTICE file | ||
# distributed with this work for additional information | ||
# regarding copyright ownership. The ASF licenses this file | ||
# to you under the Apache License, Version 2.0 (the | ||
# "License"); you may not use this file except in compliance | ||
# with the License. You may obtain a copy of the License at | ||
# | ||
# http://www.apache.org/licenses/LICENSE-2.0 | ||
# | ||
# Unless required by applicable law or agreed to in writing, | ||
# software distributed under the License is distributed on an | ||
# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY | ||
# KIND, either express or implied. See the License for the | ||
# specific language governing permissions and limitations | ||
# under the License. | ||
""" Hexagon slice cast op compute and schedule""" | ||
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from tvm import te | ||
from tvm import tir | ||
from ..utils import get_layout_transform_fn | ||
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def get_layout_transform_for_f32(f32_layout_string): | ||
""" | ||
Given f32 layout string, return transform_layout function and | ||
channel/height split factor to be used for scheduling | ||
""" | ||
layout_transform_fn = get_layout_transform_fn(f32_layout_string) | ||
if f32_layout_string == "nhwc-8h2w32c2w-2d": | ||
return [layout_transform_fn, 8] | ||
if f32_layout_string == "nhwc-4h2w32c2w-2d": | ||
return [layout_transform_fn, 4] | ||
if f32_layout_string == "nc-1024c-2d": | ||
return [layout_transform_fn, 1024] | ||
if f32_layout_string == "nc-512c-2d": | ||
return [layout_transform_fn, 512] | ||
raise RuntimeError(f"Unexpected f32_layout '{f32_layout_string}'") | ||
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def cast_f16_f32_compute(in_tensor): | ||
out_tensor = te.compute( | ||
in_tensor.shape, lambda *indices: in_tensor[indices].astype("float32"), name="CastF16F32" | ||
) | ||
return out_tensor | ||
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def cast_f16_f32_stir_schedule_nhwc(func, in_layout, out_layout, h_split_factor): | ||
"""Schedule for nhwc f16 to f32 cast: nhwc layout""" | ||
sch = tir.Schedule(func, debug_mask="all") | ||
block_name = "CastF16F32" | ||
n_orig, h_orig, w_orig, c_orig = sch.get_loops(sch.get_block(block_name)) | ||
h_outer, h_inner = sch.split(h_orig, [None, h_split_factor]) | ||
w_outer, w_inner = sch.split(w_orig, [None, 4]) | ||
c_outer, c_inner = sch.split(c_orig, [None, 32]) | ||
w_inner_o, w_inner_i = sch.split(w_inner, [None, 2]) | ||
sch.reorder(n_orig, h_outer, w_outer, c_outer, h_inner, w_inner_o, c_inner, w_inner_i) | ||
sch.transform_layout(block_name, "A", in_layout) | ||
sch.transform_layout(block_name, block_name, out_layout) | ||
fused = sch.fuse(c_inner, w_inner_i) | ||
sch.vectorize(fused) | ||
return sch | ||
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def cast_f16_f32_stir_schedule_nc(func, in_layout, out_layout, c_split_factor): | ||
"""Schedule for nc f16 to f32 cast: nc layout""" | ||
sch = tir.Schedule(func, debug_mask="all") | ||
block_name = "CastF16F32" | ||
_, c_orig = sch.get_loops(sch.get_block(block_name)) | ||
_, c_inner = sch.split(c_orig, [None, c_split_factor]) | ||
sch.transform_layout(block_name, "A", in_layout) | ||
sch.transform_layout(block_name, block_name, out_layout) | ||
sch.vectorize(c_inner) | ||
return sch | ||
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def cast_f16_f32_schedule(cast_func, in_layout_str, out_layout_str): | ||
"""Schedule for f16 to f32 cast: top level function""" | ||
f32_layout_transform_func, split_factor = get_layout_transform_for_f32(out_layout_str) | ||
f16_layout_transform_func = get_layout_transform_fn(in_layout_str) | ||
if in_layout_str == "nhwc-8h2w32c2w-2d": | ||
return cast_f16_f32_stir_schedule_nhwc( | ||
cast_func, | ||
f16_layout_transform_func, | ||
f32_layout_transform_func, | ||
split_factor, | ||
) | ||
if in_layout_str == "nc-1024c-2d": | ||
return cast_f16_f32_stir_schedule_nc( | ||
cast_func, f16_layout_transform_func, f32_layout_transform_func, split_factor | ||
) | ||
raise RuntimeError(f"Unexpected input_layout, output_layout '{input_layout, output_layout}'") | ||
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def cast_f32_f16_compute(in_tensor): | ||
out_tensor = te.compute( | ||
in_tensor.shape, lambda *indices: in_tensor[indices].astype("float16"), name="CastF32F16" | ||
) | ||
return out_tensor | ||
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def cast_f32_f16_stir_schedule_nhwc(func, in_layout, out_layout, h_split_factor): | ||
"""Schedule for nhwc f32 to f16 cast: nhwc layout""" | ||
sch = tir.Schedule(func, debug_mask="all") | ||
block_name = "CastF32F16" | ||
n_orig, h_orig, w_orig, c_orig = sch.get_loops(sch.get_block(block_name)) | ||
h_outer, h_inner = sch.split(h_orig, [None, h_split_factor]) | ||
w_outer, w_inner = sch.split(w_orig, [None, 4]) | ||
c_outer, c_inner = sch.split(c_orig, [None, 32]) | ||
w_inner_o, w_inner_i = sch.split(w_inner, [None, 2]) | ||
sch.reorder(n_orig, h_outer, w_outer, c_outer, h_inner, w_inner_o, c_inner, w_inner_i) | ||
sch.transform_layout(block_name, "A", in_layout) | ||
sch.transform_layout(block_name, block_name, out_layout) | ||
fused = sch.fuse(c_inner, w_inner_i) | ||
sch.vectorize(fused) | ||
return sch | ||
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def cast_f32_f16_stir_schedule_nc(func, in_layout, out_layout, c_split_factor): | ||
"""Schedule for nc f32 to f16 cast: nc layout""" | ||
sch = tir.Schedule(func, debug_mask="all") | ||
block_name = "CastF32F16" | ||
_, c_orig = sch.get_loops(sch.get_block(block_name)) | ||
_, c_inner = sch.split(c_orig, [None, c_split_factor]) | ||
sch.transform_layout(block_name, "A", in_layout) | ||
sch.transform_layout(block_name, block_name, out_layout) | ||
sch.vectorize(c_inner) | ||
return sch | ||
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def cast_f32_f16_schedule(cast_func, in_layout_str, out_layout_str): | ||
"""Schedule for f32 to f16 cast: top level function""" | ||
f32_layout_transform_func, split_factor = get_layout_transform_for_f32(in_layout_str) | ||
f16_layout_transform_func = get_layout_transform_fn(out_layout_str) | ||
if out_layout_str == "nhwc-8h2w32c2w-2d": | ||
return cast_f32_f16_stir_schedule_nhwc( | ||
cast_func, f32_layout_transform_func, f16_layout_transform_func, split_factor | ||
) | ||
if out_layout_str == "nc-1024c-2d": | ||
return cast_f32_f16_stir_schedule_nc( | ||
cast_func, f32_layout_transform_func, f16_layout_transform_func, split_factor | ||
) | ||
raise RuntimeError(f"Unexpected input_layout, output_layout '{in_layout_str, out_layout_str}'") |
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In the future, is this function intended to remain a mapping from string to layout function, or will it have more dynamic behavior? If the former, then it may be useful to define a dictionary instead, since that would allow tests to be parametrized over each layout.
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Hi Eric @Lunderberg , Thank you for your time and helpful inputs. I think for now we are sticking to pre-defined layouts. But we don't want the tests to be parameterized over each layout since the tests wouldn't support each one of them.