[MetaSchedule] Tile and pack intermediate output for CUDA TensorCore #14108
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Hzfengsy
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Mar 4, 2023
Co-authored-by: Siyuan Feng <Hzfengsy@sjtu.edu.cn>
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Thanks @vinx13 |
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This PR changes the meta schedule rule for CUDA tensor core. It adds additional tiling and layout transformation (pack the buffer by 16x16 accumulator shape) of the output in the shared memory. By transforming the buffer to higher rank with innermost shape of 16x16, it avoids strided access that
CompactBufferRegionandcompute_atcannot handle and reduces shared memory usage for the output