Add Arm Cortex-M0+ implementation interrupt count (#39)

Resolves #34 (Add Arm Cortex-M0+ implementation interrupt count).

configuration/release/include/picolibrary/arm/cortex/m0plus/implementation/configuration.h

@@ -29,4 +29,6 @@
 
 #define PICOLIBRARY_ARM_CORTEX_M0PLUS_IMPLEMENTATION_HAS_SYSTICK 1
 
+#define PICOLIBRARY_ARM_CORTEX_M0PLUS_IMPLEMENTATION_INTERRUPTS 32
+
 #endif // PICOLIBRARY_ARM_CORTEX_M0PLUS_IMPLEMENTATION_CONFIGURATION_H

docs/interrupt.md

@@ -4,3 +4,9 @@ Arm Cortex-M0+ interrupt facilities are defined in the
 header/source file pair.
 
 ## Table of Contents
+- [Implementation Interrupt Count](#implementation-interrupt-count)
+
+## Implementation Interrupt Count
+The `::picolibrary::Arm::Cortex::M0PLUS::Interrupt::IMPLEMENTATION_INTERRUPTS` constant
+stores the number of interrupts defined by the Arm Cortex-M0+ microcontroller
+implementation.

docs/library_configuration.md

@@ -20,6 +20,8 @@ General library configuration consists of the following macros:
   peripheral VTOR register configuration
 - `PICOLIBRARY_ARM_CORTEX_M0PLUS_IMPLEMENTATION_HAS_SYSTICK`: implementation SYSTICK
   peripheral configuration
+- `PICOLIBRARY_ARM_CORTEX_M0PLUS_IMPLEMENTATION_INTERRUPTS`: implementation interrupt
+  count
 
 These macros should be accessed via the
 [`include/picolibrary/arm/cortex/m0plus/configuration.h`](https://github.com/apcountryman/picolibrary-arm-cortex-m0plus/blob/main/include/picolibrary/arm/cortex/m0plus/configuration.h)
@@ -37,5 +39,7 @@ for the Microchip SAM D21/DA1 family of Arm Cortex-M0+ microcontrollers:
 
 #define PICOLIBRARY_ARM_CORTEX_M0PLUS_IMPLEMENTATION_HAS_SYSTICK 1
 
+#define PICOLIBRARY_ARM_CORTEX_M0PLUS_IMPLEMENTATION_INTERRUPTS 28
+
 #endif // PICOLIBRARY_ARM_CORTEX_M0PLUS_IMPLEMENTATION_CONFIGURATION_H
 ```

include/picolibrary/arm/cortex/m0plus/configuration.h

@@ -37,6 +37,10 @@
 #error "PICOLIBRARY_ARM_CORTEX_M0PLUS_IMPLEMENTATION_HAS_SYSTICK not configured"
 #endif // PICOLIBRARY_ARM_CORTEX_M0PLUS_IMPLEMENTATION_HAS_SYSTICK
 
+#ifndef PICOLIBRARY_ARM_CORTEX_M0PLUS_IMPLEMENTATION_INTERRUPTS
+#error "PICOLIBRARY_ARM_CORTEX_M0PLUS_IMPLEMENTATION_INTERRUPTS not configured"
+#endif // PICOLIBRARY_ARM_CORTEX_M0PLUS_IMPLEMENTATION_INTERRUPTS
+
 namespace picolibrary::Arm::Cortex::M0PLUS {
 } // namespace picolibrary::Arm::Cortex::M0PLUS
 

include/picolibrary/arm/cortex/m0plus/interrupt.h

@@ -23,10 +23,20 @@
 #ifndef PICOLIBRARY_ARM_CORTEX_M0PLUS_INTERRUPT_H
 #define PICOLIBRARY_ARM_CORTEX_M0PLUS_INTERRUPT_H
 
+#include <cstdint>
+
+#include "picolibrary/arm/cortex/m0plus/configuration.h"
+
 /**
  * \brief Arm Cortex-M0+ interrupt facilities.
  */
 namespace picolibrary::Arm::Cortex::M0PLUS::Interrupt {
+
+/**
+ * \brief Implementation interrupt count.
+ */
+constexpr auto IMPLEMENTATION_INTERRUPTS = std::uint_fast8_t{ PICOLIBRARY_ARM_CORTEX_M0PLUS_IMPLEMENTATION_INTERRUPTS };
+
 } // namespace picolibrary::Arm::Cortex::M0PLUS::Interrupt
 
 #endif // PICOLIBRARY_ARM_CORTEX_M0PLUS_INTERRUPT_H

source/picolibrary/arm/cortex/m0plus/interrupt.cc

@@ -21,3 +21,11 @@
  */
 
 #include "picolibrary/arm/cortex/m0plus/interrupt.h"
+
+namespace picolibrary::Arm::Cortex::M0PLUS::Interrupt {
+
+static_assert(
+    IMPLEMENTATION_INTERRUPTS <= 32,
+    "invalid PICOLIBRARY_ARM_CORTEX_M0PLUS_IMPLEMENTATION_INTERRUPTS configuration" );
+
+} // namespace picolibrary::Arm::Cortex::M0PLUS::Interrupt