best practice for testing gateware core?

[matpalm]

should i use gateware/sim/vca/tb_vca.py as a template for how to test? ( or is there a better example? )

[vk2seb]

Indeed the tb_vca.py example was created as an example for how to test a simple user core using CocoTB. For something intended to be added to this repository and ran on CI, it's the simplest way to get started.

For more advanced simulation (if the core is not too complicated and can be simulated in real-time) I have another example repository of simulating the RTL inside Verilator for real-time audio simulation inside VCVRack: https://github.com/apfelaudio/verilog-vcvrack

[matpalm]

great thanks, i'll start porting my pieces to use that...
i still have to benchmark but i think my bottleneck with tuning is going to be DSP use.