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  1. uvm_tb_pipe uvm_tb_pipe Public

    Simple testbench in System Verilog UVM.

    SystemVerilog 1 1

  2. force-riscv force-riscv Public

    Forked from openhwgroup/force-riscv

    Instruction Set Generator initially contributed by Futurewei

    C++

  3. python_ex python_ex Public

  4. SystemVerilog SystemVerilog Public

    System Verilog examples

    SystemVerilog

  5. uvm_ex uvm_ex Public