Problem with testing on bsg_dataflow modules

[lomotos10]

Hello.

Running the bsg_dataflow tests by running make in their folders (e.g. testing/bsg_dataflow/bsg_channel_narrow) results in error. I think I've installed all dependencies such as Quartus, Modelsim (as Questa), and Vivado. I've made small adjustments to the code to advance the test, but I seem to have hit a wall. Could you have a look at the results and suggest the cause of the problem? Thank you very much.

Steps I took for testing and the error messages for each steps:

• Running make on testing/bsg_dataflow/bsg_channel_narrow as is:

...
xvlog --sv  -d WIDTH_IN_P=1 -d WIDTH_OUT_P=1 ...
... 
ERROR: [VRFC 10-2989] 'width_out_lp' is not declared [/home/sungsoo/WD/basejump_stl/testing/bsg_dataflow/bsg_channel_narrow/test_bsg.v:129]
ERROR: [VRFC 10-2989] 'divisions_lp' is not declared [/home/sungsoo/WD/basejump_stl/testing/bsg_dataflow/bsg_channel_narrow/test_bsg.v:135]
ERROR: [VRFC 10-2989] 'divisions_lp' is not declared [/home/sungsoo/WD/basejump_stl/testing/bsg_dataflow/bsg_channel_narrow/test_bsg.v:140]

• make results after modifying variable names to be consistent within the testbench file:

...
xelab -debug typical -s top_sim test_bsg  
...
ERROR: [XSIM 43-4099] "/home/sungsoo/WD/basejump_stl/bsg_test/bsg_nonsynth_reset_gen.v" Line 15. Module bsg_nonsynth_reset_gen(reset_cycles_lo_
p=1,reset_cycles_hi_p=5) doesn't have a timescale but at least one module in design has a timescale.  

• make results after adding the -relax flag to xelab to bypass the above error:

...
xsim --runall top_sim | /usr/bin/tee outfile

****** xsim v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
  **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source xsim.dir/top_sim/xsim_script.tcl
# xsim {top_sim} -autoloadwcfg -runall
Vivado Simulator 2020.1
Time resolution is 1 ps
run -all
test_bsg.clock_gen with cycle_time_p          20




===========================================================
testing bsg_channel_narrow with ...
WIDTH_IN_P :           1
WIDTH_OUT_P:           1

zoop 1 01
Error: 1 lsb_to_msb_data: mismatch on input=x output=x count_r=xError:  
Time: 10 ps  Iteration: 1  Process: /test_bsg/Always114_8  Scope: test_bsg  File: /home/sungsoo/WD/basejump_stl/testing/bsg_dataflow/bsg_channel_narrow/test_bsg.v Line: 124
Error: 2 msb_to_lsb_data: mismatch on input x Error: division x
Time: 10 ps  Iteration: 1  Process: /test_bsg/Always114_8  Scope: test_bsg  File: /home/sungsoo/WD/basejump_stl/testing/bsg_dataflow/bsg_channel_narrow/test_bsg.v Line: 132
Error: 3 lsb_to_msb_deque: mismatch on input x Error: division x
Time: 10 ps  Iteration: 1  Process: /test_bsg/Always114_8  Scope: test_bsg  File: /home/sungsoo/WD/basejump_stl/testing/bsg_dataflow/bsg_channel_narrow/test_bsg.v Line: 137
Error: 4 msb_to_lsb_deque: mismatch on input x Error: division x
Time: 10 ps  Iteration: 1  Process: /test_bsg/Always114_8  Scope: test_bsg  File: /home/sungsoo/WD/basejump_stl/testing/bsg_dataflow/bsg_channel_narrow/test_bsg.v Line: 142
__________ ___________  _______________________________
\______   \\_   _____/ /   _____/\_   _____/\__    ___/
 |       _/ |    __)_  \_____  \  |    __)_   |    |  
 |    |   \ |        \ /        \ |        \  |    |  0->1 time =          0
 |____|_  //_______  //_______  //_______  /  |____|  
 ASYNC  \/         \/         \/         \/            
__________ ___________  _______________________________
\______   \\_   _____/ /   _____/\_   _____/\__    ___/
 |       _/ |    __)_  \_____  \  |    __)_   |    |  
 |    |   \ |        \ /        \ |        \  |    |  1->0 time =          0
 |____|_  //_______  //_______  //_______  /  |____|  
 ASYNC  \/         \/         \/         \/            
==========================================================

$finish called at time : 170 ps : File "/home/sungsoo/WD/basejump_stl/testing/bsg_dataflow/bsg_channel_narrow/test_bsg.v" Line 104