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Issues list

Harden buffers in bsg_link? clarity Code readability or documentation issues
#711 opened Dec 2, 2024 by dpetrisko
@dpetrisko
commone interface stl
#694 opened Sep 7, 2024 by neilwang0913
3
Broken Links
#687 opened Jun 13, 2024 by Subashkatel
1
Broken cache testbenches
#637 opened Jan 11, 2023 by BrendenPage
@farzamgl @tommydcjung
5
bsg_nonsynth_dramsim3 failing testbench bug Something isn't working
#622 opened Dec 16, 2022 by dpetrisko
bsg_cache_to_test_dram does not support multiple outstanding reads per channel bug Something isn't working
#616 opened Dec 11, 2022 by dpetrisko
@dpetrisko
1
Add code for FPGA side of bsg_link enhancement New feature or request
#609 opened Nov 15, 2022 by taylor-bsg
@gaozihou
2
bsg_cache optimization -- don't replay TL instruction if there is no TL instruction enhancement New feature or request
#586 opened Oct 1, 2022 by dpetrisko
4
Undefined parameter used when instantiating bsg_mem_1rw_sync
#577 opened Jul 2, 2022 by Yuan-Mao
1
Problem with testing on bsg_dataflow modules
#574 opened Jun 28, 2022 by lomotos10
Document on how to add and simulate PLL to bsg_chip enhancement New feature or request
#570 opened May 29, 2022 by yunusdawji
Add comment that describes difference between this SIPO and others
#558 opened Mar 1, 2022 by taylor-bsg
@dpetrisko @gaozihou
1
long term change enhancement New feature or request
#545 opened Feb 7, 2022 by taylor-bsg
Should have comment explaining when to use scan here clarity Code readability or documentation issues
#537 opened Dec 19, 2021 by dpetrisko
Hardcoded address width in bsg_cache_to_dram_ctrl bug Something isn't working
#532 opened Dec 9, 2021 by dpetrisko
1
DMC TB params : remove hardcoded values.
#520 opened Nov 1, 2021 by akashnt4
Should be yumi_o not ready_o
#517 opened Oct 27, 2021 by taylor-bsg
2
Small fifo hardened power consumption enhancement New feature or request
#512 opened Oct 21, 2021 by gaozihou
@gaozihou
2
Multiple latches clarity Code readability or documentation issues enhancement New feature or request
#497 opened Sep 26, 2021 by dpetrisko
@taylor-bsg
add parameter to clock gate the write data latch
#489 opened Aug 30, 2021 by taylor-bsg
@tommydcjung
Force bsg_cache_dma cache line alignment enhancement New feature or request
#481 opened Aug 3, 2021 by dpetrisko
ADD "U R CRAZY" warnings when attempting to synthesize things that must absolutely be hardened enhancement New feature or request
#448 opened Jun 14, 2021 by taylor-bsg
Move DMA memory modules to bsg_test enhancement New feature or request
#444 opened May 27, 2021 by mrutt92
@mrutt92
Consider (later) pulling ready low during reset.
#434 opened May 6, 2021 by taylor-bsg
Incorrect comments on v_i/ready_o port in bsg_one_fifo
#428 opened Apr 16, 2021 by muwyse
3
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