timer irq second test - reached 'mret clears' failure (exit code 3)

bieganski · Aug 18, 2024 · cf079b9 · cf079b9
1 parent 8a5bec3
commit cf079b9
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Showing 3 changed files with 8 additions and 4 deletions.
diff --git a/mtkcpu/tests/test_csr.py b/mtkcpu/tests/test_csr.py
@@ -388,7 +388,7 @@
         out_val=100,
         timeout=2000,
         mem_init=MemoryContents.empty(),
-        reg_init=RegistryContents.fill(),
+        reg_init=RegistryContents.empty(),
     ),
 ]
 

diff --git a/mtkcpu/utils/tests/sim_tests.py b/mtkcpu/utils/tests/sim_tests.py
@@ -290,7 +290,7 @@ def reg_test(timeout=default_timeout_extra + timeout_cycles, expected_val=expect
         yield Tick()
         yield Settle()
 
-        for _ in range(timeout):
+        for i in range(timeout):
             en = yield cpu.reg_write_port.en
             if en == 1:
                 addr = yield cpu.reg_write_port.addr
@@ -311,9 +311,10 @@ def reg_test(timeout=default_timeout_extra + timeout_cycles, expected_val=expect
                     if check_reg_content and cond:
                         # TODO that mechanism for now allows for only one write to observed register per test,
                         # extend it if neccessary.
+                        pc = yield cpu.pc
                         print(
                             f"== ERROR: Expected data write to reg x{addr} of value {hex(expected_val)},"
-                            f" got value {hex(val)}.. \n== fail test: {name}\n"
+                            f" got value {hex(val)} in cycle={i}, PC={hex(pc)}.. \n== fail test: {name}\n"
                         )
                         print(
                             f"{format(expected_val, '32b')} vs {format(val, '32b')}"

diff --git a/mtkcpu/utils/tests/utils.py b/mtkcpu/utils/tests/utils.py
@@ -210,6 +210,8 @@ def reg_test(
     sim.add_sync_process(capture_write_transactions(cpu=cpu, dict_reference=result_mem))
     # sim.add_sync_process(print_mem_transactions(cpu=cpu))
     sim.add_sync_process(check_addr_translation_errors(cpu=cpu))
+
+    sim.add_sync_process(monitor_pc_and_main_fsm(cpu=cpu, wait_for_first_haltreq=False, log_fn=print))
 
     sim.add_sync_process(
         get_sim_register_test(
@@ -292,7 +294,8 @@ def get_code_mem(case: MemTestCase, mem_size_kb: int) -> MemoryContents:
         import tempfile
         with tempfile.NamedTemporaryFile(
             suffix=".elf",
-            dir=Path(__file__).parent
+            dir=Path(__file__).parent,
+            delete=False
         ) as tmp_elf:
             source = f"""
             .global start