Fix: proper IR quirk handling for Xilinx FPGAs

[lethalbit]

Detailed description

This fixes potentials issues that one may run into when they have a scan-chain with an Xilinx FPGA on it, as not all Xilinx FPGAs have the 6-bit IR. The documentation such as UG570¹ states that the IR is 6-bits as a general rule of thumb, however one must consult the device specific BSDL² files in order to divine the correct IR length for any given device.

Upon consultation of the BSDL models provided by Xilinx, it is made apparent that the following IR lengths are present: 6, 12, 14, 18, 21, 22, 28, and 38. While the vast majority of the devices are in-fact 6-bit wide IR devices, the chance of encountering a device with one of the other IR lengths is reasonably high.

Rather than individually listing each device ID and it's IR length, effort has been made to reduce the device ID space into the greatest common denominators, which then uses the IR quirks machinery to ensure that the IR length is set correctly.

This should enable more robust handling of scan-chains with Xilinx FPGAs present on them.

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• I've read the Code of Conduct
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• It builds for hardware native (make PROBE_HOST=native)
• It builds as BMDA (make PROBE_HOST=hosted)
• I've tested it to the best of my ability
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Footnotes

1. https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration ↩

2. https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/device-models.html ↩