iscas89_hl_verilog

Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF", etc.)

I couldn't find this version of the ISCAS89 circuits hosted anywhere anymore. You only find the original versions that uses implicit cells, like "DFF", under http://pld.ttu.ee/~maksim/benchmarks. The URL I downloaded the ones hosted here is dead by now: https://ddd.fit.cvut.cz/prj/Benchmarks/index.php

I just upload this set of benchmarks "AS IS", because the original host is not available anymore. Please let me know if you think this is a violation of anyones rights and I can take this repository down again. I give no warranties whatsoever. Please consider citing the original paper when using them:

@inproceedings{Brglez1989,
	title={Combinational profiles of sequential benchmark circuits},
	author={Brglez, Franc and Bryan, David and Kozminski, Krzysztof},
	booktitle={IEEE International Symposium on Circuits and Systems (ISCAS)},
	pages={1929--1934},
	year={1989},
	organization={IEEE}
}

Please let me know if you think this is a violation of anyones rights and I can take this repository down again.