For discussion

cranelift-codegen/meta/src/cdsl/instructions.rs

@@ -12,7 +12,7 @@ use crate::cdsl::formats::{
 };
 use crate::cdsl::operands::Operand;
 use crate::cdsl::type_inference::Constraint;
-use crate::cdsl::types::{LaneType, ValueType};
+use crate::cdsl::types::{LaneType, ValueType, VectorType};
 use crate::cdsl::typevar::TypeVar;
 
 #[derive(Copy, Clone, PartialEq, Eq, Hash, PartialOrd, Ord)]
@@ -188,6 +188,14 @@ impl Instruction {
     pub fn bind(&self, lane_type: impl Into<LaneType>) -> BoundInstruction {
         bind(self.clone(), Some(lane_type.into()), Vec::new())
     }
+
+    pub fn bind_vector(&self, lane_type: impl Into<LaneType>, num_lanes: u64) -> BoundInstruction {
+        let vector_type = ValueType::Vector(VectorType::new(lane_type.into(), num_lanes));
+        let value_types = vec![ValueTypeOrAny::ValueType(vector_type)];
+        verify_polymorphic_binding(self, &value_types);
+        BoundInstruction { inst: self.clone(), value_types }
+    }
+
     pub fn bind_any(&self) -> BoundInstruction {
         bind(self.clone(), None, Vec::new())
     }
@@ -1078,6 +1086,16 @@ fn bind(
         }
     }
 
+    verify_polymorphic_binding(&inst, &value_types);
+
+    BoundInstruction { inst, value_types }
+}
+
+/// Helper to verify that binding types to the instruction does not violate polymorphic rules
+fn verify_polymorphic_binding(
+    inst: &Instruction,
+    value_types: &Vec<ValueTypeOrAny>,
+) {
     match &inst.polymorphic_info {
         Some(poly) => {
             assert!(
@@ -1092,6 +1110,4 @@ fn bind(
             ));
         }
     }
-
-    BoundInstruction { inst, value_types }
 }

cranelift-codegen/meta/src/isa/x86/encodings.rs

@@ -377,6 +377,7 @@ pub fn define(
     let x86_fmax = x86.by_name("x86_fmax");
     let x86_fmin = x86.by_name("x86_fmin");
     let x86_pop = x86.by_name("x86_pop");
+    let x86_pshuf = x86.by_name("x86_pshuf");
     let x86_push = x86.by_name("x86_push");
     let x86_sdivmodx = x86.by_name("x86_sdivmodx");
     let x86_smulx = x86.by_name("x86_smulx");
@@ -520,6 +521,10 @@ pub fn define(
     // Definitions.
     let mut e = PerCpuModeEncodings::new();
 
+    // x86 requires a data move to the XMM registers which is part of legalize.rs; this simply implements the shuffling of bits
+    e.enc32(x86_pshuf.bind_vector(I32, 4), r.template("splat").nonrex().opcodes(vec![0x66, 0x0f, 0x70]));
+    e.enc64(x86_pshuf.bind_vector(I32, 4), r.template("splat").nonrex().opcodes(vec![0x66, 0x0f, 0x70]));
+
     e.enc_i32_i64(iadd, rec_rr.opcodes(vec![0x01]));
     e.enc_i32_i64(isub, rec_rr.opcodes(vec![0x29]));
     e.enc_i32_i64(band, rec_rr.opcodes(vec![0x21]));

cranelift-codegen/meta/src/isa/x86/instructions.rs

@@ -249,5 +249,32 @@ pub fn define(
         .operands_out(vec![y, rflags]),
     );
 
+    let TxN = &TypeVar::new(
+        "TxN",
+        "A SIMD vector type",
+        TypeSetBuilder::new()
+            .ints(Interval::All)
+            .floats(Interval::All)
+            .bools(Interval::All)
+            .simd_lanes(Interval::All)
+            .includes_scalars(false)
+            .build(),
+    );
+    let a = &operand("a", TxN);
+    //let b = &operand("b", TxN);
+    ig.push(
+        Inst::new(
+            "x86_pshuf",
+            r#"
+    Shuffle Packed -- copies data from either memory or lanes in an extended
+    register and re-orders the data according to the passed immediate byte.
+    TODO allow memory type here
+    TODO how to allow passing in immediate during code generation?
+    "#,
+        )
+            .operands_in(vec![a])
+            .operands_out(vec![a]),
+    );
+
     ig.build()
 }

cranelift-codegen/meta/src/isa/x86/legalize.rs

@@ -19,6 +19,7 @@ pub fn define(shared: &mut SharedDefinitions, x86_instructions: &InstructionGrou
     // List of instructions.
     let insts = &shared.instructions;
     let band = insts.by_name("band");
+    let bitcast = insts.by_name("bitcast");
     let bor = insts.by_name("bor");
     let clz = insts.by_name("clz");
     let ctz = insts.by_name("ctz");
@@ -38,6 +39,7 @@ pub fn define(shared: &mut SharedDefinitions, x86_instructions: &InstructionGrou
     let sdiv = insts.by_name("sdiv");
     let selectif = insts.by_name("selectif");
     let smulhi = insts.by_name("smulhi");
+    let splat = insts.by_name("splat");
     let srem = insts.by_name("srem");
     let udiv = insts.by_name("udiv");
     let umulhi = insts.by_name("umulhi");
@@ -46,6 +48,7 @@ pub fn define(shared: &mut SharedDefinitions, x86_instructions: &InstructionGrou
 
     let x86_bsf = x86_instructions.by_name("x86_bsf");
     let x86_bsr = x86_instructions.by_name("x86_bsr");
+    let x86_pshuf = x86_instructions.by_name("x86_pshuf");
     let x86_umulx = x86_instructions.by_name("x86_umulx");
     let x86_smulx = x86_instructions.by_name("x86_smulx");
 
@@ -82,6 +85,15 @@ pub fn define(shared: &mut SharedDefinitions, x86_instructions: &InstructionGrou
         vec![def!((res_lo, res_hi) = x86_smulx(x, y))],
     );
 
+    // SIMD
+//    group.legalize(
+//        def!(y = splat(x)),
+//        vec![
+//            def!(a = bitcast(x)),
+//            def!(y = x86_pshuf(a))
+//        ]
+//    );
+
     // Floating point condition codes.
     //
     // The 8 condition codes in `supported_floatccs` are directly supported by a

cranelift-codegen/meta/src/isa/x86/recipes.rs

@@ -481,6 +481,21 @@ pub fn define<'shared>(
             ),
     );
 
+    {
+        recipes.add_template_recipe(
+            EncodingRecipeBuilder::new("splat", f_unary, 2)
+                .operands_in(vec![fpr])
+                .operands_out(vec![fpr])
+                .emit(
+                    r#"
+                    {{PUT_OP}}(bits, rex2(in_reg0, out_reg0), sink);
+                    modrm_rr(in_reg0, out_reg0, sink);
+                    sink.put1(0);
+                "#,
+                ),
+        );
+    }
+
     // XX /r with operands swapped. (RM form).
     recipes.add_template_recipe(
         EncodingRecipeBuilder::new("rrx", f_binary, 1)

filetests/isa/x86/simd.clif

@@ -0,0 +1,23 @@
+test binemit
+; set opt_level=best
+target x86_64
+
+; The binary encodings can be verified with the command:
+;
+;   sed -ne 's/^ *; asm: *//p' filetests/isa/x86/shrink.clif | llvm-mc -show-encoding -triple=x86_64
+;
+
+; run with `target/debug/clif-util test -v filetests/isa/x86/simd.clif`
+;function %test_simple() {
+;ebb0:
+;    [RexOp1pu_id#b8, %rax]  v1 = iconst.i32 42  ; bin: 40 b8 0000002a
+;    [Op1pu_id#b8, %rax]     v2 = iconst.i32 42  ; bin: b8 0000002a
+;    [Op1ret#c3]             return              ; bin: c3
+;}
+
+function %test_simd() {
+ebb0:
+[-, %rax]   v0 = iconst.i32 42
+[-, %xmm0]  v1 = splat.i32x4 v0     ; bin: 66 0f 70 c0 00
+            return
+}