Lab3 multipler and adder speed

[Charlee0207]

大家好
小弟不才我在設定clock period時，發現在FIR中若在同個clock中使用multiplier及adder如下
shift <= tap*data;
accumulation <= accumulation + shift;

即便我用pipeline將乘加運算分開賦值給兩個register
total delay還是比在同個clock中只使用multiplier或adder增加約6ns

想請問如果不是小弟犯蠢哪裡寫錯
還能如何增加在同個clock使用multiplier及adder的速度呢？謝謝！

// with multiplier and adder, total delay ~= 10ns
always@(posedge clk)begin
    if(!rst_n) accumulation <= 0;
    /*other condition*/
    else begin
        shift <= tap*data;
        accumulation <= accumulation + shift;
    end
end

// only with adder , total delay < 4ns
always@(posedge clk)begin
    if(!rst_n) accumulation <= 0;
    /*other condition*/
    else begin
        shift <= tap*data;
        accumulation <= accumulation;
    end
end

[JackeyUi]

如果你的 shift 值沒有其他特別用處的話，試試看直接縮成一行

accmulation <= accumulation + tap * data

[Charlee0207]

謝謝你的回覆！
我試過寫在同一行，但結果delay變得更長：（

[chickenchennnn]

請問你有看過你兩種不同Design下的critical path是哪一條嗎

[boledulab]

Your coding style is more like HLS. Logic synthesis tool is not capable of doing pipeline partition. I will suggest you write rtl code in a structure way. Otherwise, you really can not control the timing and speed you want.

module mult (a, b, c ) // you may use pipeline multiplier based on the speed you need
assign c = a * b;
endmodule

module add (a, b, c) // you may use pipeline adder based on the speed you need
assign c = a + b;
endmodule

in main module,

// acc = acc + a * b;
mult mult_instance(a, b, d_c);
r_c = d_c @ clock ; // pipe register
add add_instance(acc, r_c, d_acc);
acc = d_acc @ clock； // pipe register

note: if you use pipeline multiplier , adder (# of stages), design the controller timing accordingly.
note: the pipeline of multiplier and adder depends on the speed you need, and balance with other logic, e.g. SRAM access timing.