Lab-D Change linker

[Yanlin900414]

Adjust linear address map below, so that code execution and data fetch are from two different banks .
想請問一下這個Lab的PDF中上述這段話的詳細意思，依照說明是使用matmul.hex來實作這個Lab，但是我看他每次乘完後的值都是直接存在RISC-V內部，最後算出來直接輸出(0x3e 0x44 0x4A 0x50)，中間運算出來的值並不會回傳至Sdram，Sdram內部只有一堆執行Matmul的指令，因此不確定上述提到的data是指什麼。

[boledulab]

Refer to sections.lds; both .data and .bss are allocated in the dff region. We can relocated to mprjram. Try it out and see if the data access is from/to mprjram. Check the variables location from the assembly code, then, see if we can adjust the SDRAM controller linear mapped address to bank / row decoding.
MEMORY {
vexriscv_debug : ORIGIN = 0xf00f0000, LENGTH = 0x00000100
dff : ORIGIN = 0x00000000, LENGTH = 0x00000400
dff2 : ORIGIN = 0x00000400, LENGTH = 0x00000200
flash : ORIGIN = 0x10000000, LENGTH = 0x01000000
mprj : ORIGIN = 0x30000000, LENGTH = 0x00100000
mprjram : ORIGIN = 0x38000000, LENGTH = 0x00400000
hk : ORIGIN = 0x26000000, LENGTH = 0x00100000
CSR : ORIGIN = 0xf0000000, LENGTH = 0x00010000
}
.data :
{
. = ALIGN(8);
_fdata = .;
(.data .data. .gnu.linkonce.d.*)
(.data1)
_gp = ALIGN(16);
(.sdata .sdata. .gnu.linkonce.s.)
. = ALIGN(8);
_edata = .;
} > dff AT > flash

.bss :
{
	. = ALIGN(8);
	_fbss = .;
	*(.dynsbss)
	*(.sbss .sbss.* .gnu.linkonce.sb.*)
	*(.scommon)
	*(.dynbss)
	*(.bss .bss.* .gnu.linkonce.b.*)
	*(COMMON)
	. = ALIGN(8);
	_ebss = .;
	_end = .;
} > dff AT > flash

[Yanlin900414]

好的了解，謝謝 !