Lab6 FPGA上模擬出現亂碼 #162
Lab6 FPGA上模擬出現亂碼
#162
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想請問一下在firmware模擬時是傳送一個TEST的字串，模擬也成功，但到了FPGA卻出現亂碼，想了解一下這是甚麼原因造成的，謝謝! |
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Answered by
LingChiYang
Dec 4, 2023
Replies: 1 comment 1 reply
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同學好 會出現亂碼是因為收回來的資料錯誤，可以請同學先確認模擬時tx rx是不是同一筆資料 |
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1 reply
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後來有發現不是同一筆資料是因為有不小心修改到mprj_io[6]，才會造成錯誤，目前已解決，謝謝助教! |
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Answer selected by
Alex17898
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同學好
會出現亂碼是因為收回來的資料錯誤，可以請同學先確認模擬時tx rx是不是同一筆資料