-
We are currently working on a part of our final project. The figure below shows the block diagram of our entire project. To reduce hardware & software overhead, we plan to use the Mailbox (MB) on the FPGA side to generate an interrupt service routine to inform the PS side that our data is ready. However, we are still not sure how to implement this part (FPGA to PS side ISR). I would appreciate any guidance from those who know how to do this. |
Beta Was this translation helpful? Give feedback.
Replies: 2 comments 2 replies
-
Hi Vic,
Following images is my experiment before that connect AXI_UART LITE IP to PS via interrupt controller and using Python asyncio library to handler it's interrupt. |
Beta Was this translation helpful? Give feedback.
-
Hi vic9112, May be the aa_mb_irq can coonect to a input of GPIO controller, and enabling the GPIO input interrupt, the ISR can be hooked to GPIO interrupt. Below is Xilinx Zynq Vivado GPIO Interrupt Example for reference |
Beta Was this translation helpful? Give feedback.
Hi Vic,
You can't add a new ISR directly in python code.
PYNQ have a guide to introduce how to handle the interrupt which came from PL in PS python code:
https://pynq.readthedocs.io/en/latest/pynq_libraries/interrupt.html
To achieve your requirement, the procedure may need:
Note: Must make sure the property of controller is configured correctly according the guide. Example: Set Interrupt type from Level to Edge.