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Refer to lecture ppt: interconnect io cache access.
In FSIC architecture, the mailbox is defined for inter-processor communication, Caravel/RISC-V, and FPGA/PS. The communication mechanism is below - take an example that Caravel/RISC-V sends a message to FPGA/PS
RISC-V write to mailbox in Caravel
Mailbox sends the message to the other side, i.e., mailbox in the FPGA side
FPGA mailbox raises an interrupt
FPGA/PS read the mailbox content
The mailbox is hardware accessed by memory-mapped IO. It takes a longer time to access IO.
To reduce the overhead, we can direct the mailbox hardware to send the message to CPU cache, so the FPGA/PS CPU can read the mailbox content from local cache. It greatly facilitate the processor-to-processor communication.
[ interconnect-io-cache-access.pdf
]
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Refer to lecture ppt: interconnect io cache access.
In FSIC architecture, the mailbox is defined for inter-processor communication, Caravel/RISC-V, and FPGA/PS. The communication mechanism is below - take an example that Caravel/RISC-V sends a message to FPGA/PS
The mailbox is hardware accessed by memory-mapped IO. It takes a longer time to access IO.
To reduce the overhead, we can direct the mailbox hardware to send the message to CPU cache, so the FPGA/PS CPU can read the mailbox content from local cache. It greatly facilitate the processor-to-processor communication.
[
interconnect-io-cache-access.pdf
]
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