Lab2 - Error when running co-simulation

[gene5487]

Hello everyone,

I encountered the errors while attempting to run co-simulation for FIR (fir_n11_maxi) in Vits HLS during the implementation of Lab2.
I'm not sure how to solve it. Any help would be greatly appreciated.

Here's the log of my co-simulation:

Starting C/RTL cosimulation ...
/tools/Xilinx/Vitis_HLS/2022.1/bin/vitis_hls /home/ubuntu/Desktop/course-lab_2-2022.1/vitis_hls_project/hls_ip_fir/solution1/cosim.tcl
INFO: [HLS 200-10] Running '/tools/Xilinx/Vitis_HLS/2022.1/bin/unwrapped/lnx64.o/vitis_hls'
INFO: [HLS 200-10] For user 'ubuntu' on host 'ubuntu2004.linuxvmimages.local' (Linux_x86_64 version 5.15.0-76-generic) on Thu Sep 14 09:09:04 EDT 2023
INFO: [HLS 200-10] On os Ubuntu 20.04.4 LTS
INFO: [HLS 200-10] In directory '/home/ubuntu/Desktop/course-lab_2-2022.1/vitis_hls_project'
Sourcing Tcl script '/home/ubuntu/Desktop/course-lab_2-2022.1/vitis_hls_project/hls_ip_fir/solution1/cosim.tcl'
INFO: [HLS 200-1510] Running: source /home/ubuntu/Desktop/course-lab_2-2022.1/vitis_hls_project/hls_ip_fir/solution1/cosim.tcl
INFO: [HLS 200-1510] Running: open_project hls_ip_fir
INFO: [HLS 200-10] Opening project '/home/ubuntu/Desktop/course-lab_2-2022.1/vitis_hls_project/hls_ip_fir'.
INFO: [HLS 200-1510] Running: set_top fir_n11_maxi
INFO: [HLS 200-1510] Running: add_files ../hls_FIRN11MAXI/FIR.cpp
INFO: [HLS 200-10] Adding design file '../hls_FIRN11MAXI/FIR.cpp' to the project
INFO: [HLS 200-1510] Running: add_files ../hls_FIRN11MAXI/FIR.h
INFO: [HLS 200-10] Adding design file '../hls_FIRN11MAXI/FIR.h' to the project
INFO: [HLS 200-1510] Running: add_files -tb ../hls_FIRN11MAXI/FIRTester.cpp
INFO: [HLS 200-10] Adding test bench file '../hls_FIRN11MAXI/FIRTester.cpp' to the project
INFO: [HLS 200-1510] Running: open_solution solution1 -flow_target vivado
INFO: [HLS 200-10] Opening solution '/home/ubuntu/Desktop/course-lab_2-2022.1/vitis_hls_project/hls_ip_fir/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-1611] Setting target device to 'xc7z020-clg400-1'
INFO: [HLS 200-1505] Using flow_target 'vivado'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2022.1;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-1510] Running: set_part xc7z020clg400-1
INFO: [HLS 200-1510] Running: create_clock -period 10 -name default
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-1510] Running: cosim_design -trace_level all
INFO: [COSIM 212-47] Using XSIM for RTL simulation.
INFO: [COSIM 212-14] Instrumenting C test bench ...
Build using "/tools/Xilinx/Vitis_HLS/2022.1/tps/lnx64/gcc-8.3.0/bin/g++"
Compiling FIRTester.cpp_pre.cpp.tb.cpp
Compiling FIR.cpp_pre.cpp.tb.cpp
Compiling apatb_fir_n11_maxi.cpp
Compiling apatb_fir_n11_maxi_ir.ll
Generating cosim.tv.exe
INFO: [COSIM 212-302] Starting C TB testing ...
Start test!
ERROR: System recieved a signal named SIGSEGV and the program has to stop immediately!
This signal was generated when a program tries to read or write outside the memory that is allocated for it, or to write memory that can only be read.
Possible cause of this problem may be: 1) the depth setting of pointer type argument is much larger than it needed; 2)insufficient depth of array argument; 3)null pointer etc.
Current execution stopped during CodeState = DELETE_CHAR_BUFFERS.
You can search CodeState variable name in apatb*.cpp file under ./sim/wrapc dir to locate the position.
ERROR: [COSIM 212-360] Aborting co-simulation: C TB simulation failed.
ERROR: [COSIM 212-320] C TB testing failed, stop generating test vectors. Please check C TB or re-run cosim.
ERROR: [COSIM 212-5] *** C/RTL co-simulation file generation failed. ***
ERROR: [COSIM 212-4] *** C/RTL co-simulation finished: FAIL ***
INFO: [HLS 200-111] Finished Command cosim_design CPU user time: 5.63 seconds. CPU system time: 2.7 seconds. Elapsed time: 9.22 seconds; current allocated memory: 8.793 MB.
command 'ap_source' returned error code
while executing
"source /home/ubuntu/Desktop/course-lab_2-2022.1/vitis_hls_project/hls_ip_fir/solution1/cosim.tcl"
invoked from within
"hls::main /home/ubuntu/Desktop/course-lab_2-2022.1/vitis_hls_project/hls_ip_fir/solution1/cosim.tcl"
("uplevel" body line 1)
invoked from within
"uplevel 1 hls::main {*}$newargs"
(procedure "hls_proc" line 16)
invoked from within
"hls_proc [info nameofexecutable] $argv"
INFO: [HLS 200-112] Total CPU user time: 7.24 seconds. Total CPU system time: 9.22 seconds. Total elapsed time: 17.93 seconds; peak allocated memory: 471.258 MB.
Finished C/RTL cosimulation.

2023/09/14 23:22 update:
I found that the error occurs when executing this line in FIRTester.cpp:
fir_n11_maxi(input, output, taps, NUM_SAMPLES * sizeof(int32_t));
If I edit the argument "NUM_SAMPLES * sizeof(int32_t)" to "NUM_SAMPLES", then the co-simulation would finish without error.
I think this error is related to pointer out of bound, but weird thing is the C simulation would finish without error even if I didn't edit that argument.

[boledulab]

Refer to the attached, see if it helps.
hls-cosim-guideline.pptx

[gene5487]

Thanks to the quick reply! I will take a look at it.

[gene5487]

Hello everyone,
I followed the instruction in Lab2 workbook section 1.2.2. Vitis Directive controls.
After setting the directives, re-run C synthesis and co-simulation, now the problem is solved!

[boledulab]

Do you know how it is solved?

[PTXTP]

I still have this problem. I set depth to 800 (over 600).
`INFO: [Common 17-206] Exiting xsim at Tue Sep 19 18:49:33 2023...
INFO: [COSIM 212-316] Starting C post checking ...

Start test!
ERROR: System recieved a signal named SIGSEGV and the program has to stop immediately!
This signal was generated when a program tries to read or write outside the memory that is allocated for it, or to write memory that can only be read.
Possible cause of this problem may be: 1) the depth setting of pointer type argument is much larger than it needed; 2)insufficient depth of array argument; 3)null pointer etc.
Current execution stopped during CodeState = ENTER_WRAPC_PC.
You can search CodeState variable name in apatb*.cpp file under ./sim/wrapc dir to locate the position.

ERROR: [COSIM 212-379] Detected segmentation violation, please check C tb.
ERROR: [COSIM 212-362] Aborting co-simulation: C TB post check failed.
ERROR: [COSIM 212-4] *** C/RTL co-simulation finished: FAIL ***`

The directives setting is look like
`set_directive_interface -mode m_axi -depth 800 -offset slave "fir_n11_maxi" pn32HPOutput

set_directive_interface -mode s_axilite "fir_n11_maxi" an32Coef

set_directive_interface -mode s_axilite "fir_n11_maxi" regXferLeng

set_directive_interface -mode m_axi -depth 800 -offset slave "fir_n11_maxi" pn32HPInput

set_directive_interface -mode s_axilite -depth 800 "fir_n11_maxi"

`
Thanks

[Yanlin900414]

Try to set depth = 600, don't set it 800 , because you just have 600 samples, maybe it will be ok.

[PTXTP]

Thanks, setting depth = 600 is ok.
INFO: [COSIM 212-1000] *** C/RTL co-simulation finished: PASS ***

[boledulab]

Refer to:
https://support.xilinx.com/s/article/60314?language=en_US
The -depth needs to be set the same as the size of the test data.
To support variable-size inputs, the Author suggests just allocating a maximum-size array, setting the depth to that size, and then just using a small section of that.