simpler internal spi clock routing

brilliantlabsAR · Nov 8, 2024 · 6132d8a · 6132d8a
1 parent e014d99
commit 6132d8a
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/source/fpga/top.sv b/source/fpga/top.sv
@@ -235,7 +235,8 @@ The primary clock sources that can connect to the primary clock routing are:
 */
 logic spi_clock_en_n;
 logic spi_clock_gate_en /* synthesis syn_keep=1 nomerge="" */;
-always_comb spi_clock_gate_en = ~(spi_clock_en_n & spi_select_in);  // trying to make this foolproof
+//always_comb spi_clock_gate_en = ~(spi_clock_en_n & spi_select_in);  // trying to make this foolproof
+always_comb spi_clock_gate_en = 1;
 always_comb spi_clock = spi_clock_in & spi_clock_gate_en;
 
 spi_peripheral spi_peripheral (