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riscv64: Optimize uadd_overflow_trap lowering (#7132)
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This commit removes the usage of `gen_icmp` in `uadd_overflow_trap`.
The comparison previously done with an explicit comparison is now
bundled directly into the conditional branch to go to the trap itself.
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@alexcrichton
alexcrichton authored Oct 2, 2023
1 parent 233786c commit 56e8481
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Showing 10 changed files with 201 additions and 235 deletions.
3 changes: 1 addition & 2 deletions cranelift/codegen/src/isa/riscv64/lower.isle
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Expand Up @@ -304,8 +304,7 @@

(rule 1 (lower (has_type $I64 (uadd_overflow_trap x y tc)))
(let ((tmp XReg (rv_add x y))
(test XReg (gen_icmp (IntCC.UnsignedLessThan) tmp x $I64))
(_ InstOutput (gen_trapnz test tc)))
(_ InstOutput (gen_trapif (IntCC.UnsignedLessThan) tmp x tc)))
tmp))

;;;; Rules for `isub` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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53 changes: 18 additions & 35 deletions cranelift/filetests/filetests/isa/riscv64/uadd_overflow_trap.clif
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Expand Up @@ -104,22 +104,17 @@ block0(v0: i64):
; VCode:
; block0:
; mv a1,a0
; li a4,127
; add a0,a1,a4
; ult a5,a0,a1##ty=i64
; trap_if user0##(a5 ne zero)
; li a3,127
; add a0,a1,a3
; trap_if user0##(a0 ult a1)
; ret
;
; Disassembled:
; block0: ; offset 0x0
; mv a1, a0
; addi a4, zero, 0x7f
; add a0, a1, a4
; bgeu a0, a1, 0xc
; addi a5, zero, 1
; j 8
; mv a5, zero
; beqz a5, 8
; addi a3, zero, 0x7f
; add a0, a1, a3
; bgeu a0, a1, 8
; .byte 0x00, 0x00, 0x00, 0x00 ; trap: user0
; ret

Expand All @@ -132,21 +127,16 @@ block0(v0: i64):

; VCode:
; block0:
; li a4,127
; add a0,a4,a0
; ult a5,a0,a4##ty=i64
; trap_if user0##(a5 ne zero)
; li a3,127
; add a0,a3,a0
; trap_if user0##(a0 ult a3)
; ret
;
; Disassembled:
; block0: ; offset 0x0
; addi a4, zero, 0x7f
; add a0, a4, a0
; bgeu a0, a4, 0xc
; addi a5, zero, 1
; j 8
; mv a5, zero
; beqz a5, 8
; addi a3, zero, 0x7f
; add a0, a3, a0
; bgeu a0, a3, 8
; .byte 0x00, 0x00, 0x00, 0x00 ; trap: user0
; ret

Expand All @@ -158,23 +148,16 @@ block0(v0: i64, v1: i64):

; VCode:
; block0:
; add a3,a0,a1
; mv a1,a3
; ult a5,a1,a0##ty=i64
; mv a0,a1
; trap_if user0##(a5 ne zero)
; mv a5,a0
; add a0,a5,a1
; trap_if user0##(a0 ult a5)
; ret
;
; Disassembled:
; block0: ; offset 0x0
; add a3, a0, a1
; mv a1, a3
; bgeu a1, a0, 0xc
; addi a5, zero, 1
; j 8
; mv a5, zero
; mv a0, a1
; beqz a5, 8
; mv a5, a0
; add a0, a5, a1
; bgeu a0, a5, 8
; .byte 0x00, 0x00, 0x00, 0x00 ; trap: user0
; ret

40 changes: 19 additions & 21 deletions ...asm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat
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Expand Up @@ -41,21 +41,20 @@

;; function u0:0:
;; block0:
;; slli a3,a0,32
;; srli a3,a3,32
;; slli a0,a0,32
;; srli a3,a0,32
;; ld a4,[const(1)]
;; add a4,a3,a4
;; ult a5,a4,a3##ty=i64
;; trap_if heap_oob##(a5 ne zero)
;; trap_if heap_oob##(a4 ult a3)
;; ld a5,8(a2)
;; ugt a4,a4,a5##ty=i64
;; bne a4,zero,taken(label3),not_taken(label1)
;; block1:
;; ld a4,0(a2)
;; add a4,a4,a3
;; ld a5,[const(0)]
;; add a4,a4,a5
;; sw a1,0(a4)
;; add a3,a4,a3
;; ld a4,[const(0)]
;; add a3,a3,a4
;; sw a1,0(a3)
;; j label2
;; block2:
;; ret
Expand All @@ -64,21 +63,20 @@
;;
;; function u0:1:
;; block0:
;; slli a2,a0,32
;; srli a3,a2,32
;; ld a2,[const(1)]
;; add a2,a3,a2
;; ult a4,a2,a3##ty=i64
;; trap_if heap_oob##(a4 ne zero)
;; slli a0,a0,32
;; srli a2,a0,32
;; ld a3,[const(1)]
;; add a3,a2,a3
;; trap_if heap_oob##(a3 ult a2)
;; ld a4,8(a1)
;; ugt a4,a2,a4##ty=i64
;; bne a4,zero,taken(label3),not_taken(label1)
;; ugt a3,a3,a4##ty=i64
;; bne a3,zero,taken(label3),not_taken(label1)
;; block1:
;; ld a4,0(a1)
;; add a4,a4,a3
;; ld a5,[const(0)]
;; add a4,a4,a5
;; lw a0,0(a4)
;; ld a3,0(a1)
;; add a3,a3,a2
;; ld a4,[const(0)]
;; add a3,a3,a4
;; lw a0,0(a3)
;; j label2
;; block2:
;; ret
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40 changes: 19 additions & 21 deletions ...wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat
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Expand Up @@ -41,21 +41,20 @@

;; function u0:0:
;; block0:
;; slli a3,a0,32
;; srli a3,a3,32
;; slli a0,a0,32
;; srli a3,a0,32
;; ld a4,[const(1)]
;; add a4,a3,a4
;; ult a5,a4,a3##ty=i64
;; trap_if heap_oob##(a5 ne zero)
;; trap_if heap_oob##(a4 ult a3)
;; ld a5,8(a2)
;; ugt a4,a4,a5##ty=i64
;; bne a4,zero,taken(label3),not_taken(label1)
;; block1:
;; ld a4,0(a2)
;; add a4,a4,a3
;; ld a5,[const(0)]
;; add a4,a4,a5
;; sb a1,0(a4)
;; add a3,a4,a3
;; ld a4,[const(0)]
;; add a3,a3,a4
;; sb a1,0(a3)
;; j label2
;; block2:
;; ret
Expand All @@ -64,21 +63,20 @@
;;
;; function u0:1:
;; block0:
;; slli a2,a0,32
;; srli a3,a2,32
;; ld a2,[const(1)]
;; add a2,a3,a2
;; ult a4,a2,a3##ty=i64
;; trap_if heap_oob##(a4 ne zero)
;; slli a0,a0,32
;; srli a2,a0,32
;; ld a3,[const(1)]
;; add a3,a2,a3
;; trap_if heap_oob##(a3 ult a2)
;; ld a4,8(a1)
;; ugt a4,a2,a4##ty=i64
;; bne a4,zero,taken(label3),not_taken(label1)
;; ugt a3,a3,a4##ty=i64
;; bne a3,zero,taken(label3),not_taken(label1)
;; block1:
;; ld a4,0(a1)
;; add a4,a4,a3
;; ld a5,[const(0)]
;; add a4,a4,a5
;; lbu a0,0(a4)
;; ld a3,0(a1)
;; add a3,a3,a2
;; ld a4,[const(0)]
;; add a3,a3,a4
;; lbu a0,0(a3)
;; j label2
;; block2:
;; ret
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72 changes: 35 additions & 37 deletions ...sm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat
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Expand Up @@ -42,51 +42,49 @@
;; function u0:0:
;; block0:
;; slli a3,a0,32
;; srli a4,a3,32
;; ld a3,[const(1)]
;; add a3,a4,a3
;; ult a5,a3,a4##ty=i64
;; trap_if heap_oob##(a5 ne zero)
;; srli a3,a3,32
;; ld a4,[const(1)]
;; add a4,a3,a4
;; trap_if heap_oob##(a4 ult a3)
;; ld a5,8(a2)
;; ugt a5,a3,a5##ty=i64
;; ld a0,0(a2)
;; add a4,a0,a4
;; ld a0,[const(0)]
;; add a4,a4,a0
;; li a0,0
;; sltu a5,zero,a5
;; sub a2,zero,a5
;; and a3,a0,a2
;; not a5,a2
;; and a2,a4,a5
;; or a3,a3,a2
;; sw a1,0(a3)
;; ugt a4,a4,a5##ty=i64
;; ld a5,0(a2)
;; add a3,a5,a3
;; ld a5,[const(0)]
;; add a3,a3,a5
;; li a5,0
;; sltu a4,zero,a4
;; sub a0,zero,a4
;; and a2,a5,a0
;; not a4,a0
;; and a0,a3,a4
;; or a2,a2,a0
;; sw a1,0(a2)
;; j label1
;; block1:
;; ret
;;
;; function u0:1:
;; block0:
;; slli a2,a0,32
;; srli a4,a2,32
;; ld a3,[const(1)]
;; add a2,a4,a3
;; ult a5,a2,a4##ty=i64
;; trap_if heap_oob##(a5 ne zero)
;; ld a5,8(a1)
;; ugt a5,a2,a5##ty=i64
;; ld a0,0(a1)
;; add a4,a0,a4
;; ld a0,[const(0)]
;; add a4,a4,a0
;; li a0,0
;; sltu a5,zero,a5
;; sub a1,zero,a5
;; and a3,a0,a1
;; not a5,a1
;; and a1,a4,a5
;; or a3,a3,a1
;; lw a0,0(a3)
;; srli a3,a2,32
;; ld a2,[const(1)]
;; add a2,a3,a2
;; trap_if heap_oob##(a2 ult a3)
;; ld a4,8(a1)
;; ugt a4,a2,a4##ty=i64
;; ld a5,0(a1)
;; add a3,a5,a3
;; ld a5,[const(0)]
;; add a3,a3,a5
;; li a5,0
;; sltu a4,zero,a4
;; sub a0,zero,a4
;; and a2,a5,a0
;; not a4,a0
;; and a0,a3,a4
;; or a2,a2,a0
;; lw a0,0(a2)
;; j label1
;; block1:
;; ret
72 changes: 35 additions & 37 deletions ...asm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat
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Original file line number Diff line number Diff line change
Expand Up @@ -42,51 +42,49 @@
;; function u0:0:
;; block0:
;; slli a3,a0,32
;; srli a4,a3,32
;; ld a3,[const(1)]
;; add a3,a4,a3
;; ult a5,a3,a4##ty=i64
;; trap_if heap_oob##(a5 ne zero)
;; srli a3,a3,32
;; ld a4,[const(1)]
;; add a4,a3,a4
;; trap_if heap_oob##(a4 ult a3)
;; ld a5,8(a2)
;; ugt a5,a3,a5##ty=i64
;; ld a0,0(a2)
;; add a4,a0,a4
;; ld a0,[const(0)]
;; add a4,a4,a0
;; li a0,0
;; sltu a5,zero,a5
;; sub a2,zero,a5
;; and a3,a0,a2
;; not a5,a2
;; and a2,a4,a5
;; or a3,a3,a2
;; sb a1,0(a3)
;; ugt a4,a4,a5##ty=i64
;; ld a5,0(a2)
;; add a3,a5,a3
;; ld a5,[const(0)]
;; add a3,a3,a5
;; li a5,0
;; sltu a4,zero,a4
;; sub a0,zero,a4
;; and a2,a5,a0
;; not a4,a0
;; and a0,a3,a4
;; or a2,a2,a0
;; sb a1,0(a2)
;; j label1
;; block1:
;; ret
;;
;; function u0:1:
;; block0:
;; slli a2,a0,32
;; srli a4,a2,32
;; ld a3,[const(1)]
;; add a2,a4,a3
;; ult a5,a2,a4##ty=i64
;; trap_if heap_oob##(a5 ne zero)
;; ld a5,8(a1)
;; ugt a5,a2,a5##ty=i64
;; ld a0,0(a1)
;; add a4,a0,a4
;; ld a0,[const(0)]
;; add a4,a4,a0
;; li a0,0
;; sltu a5,zero,a5
;; sub a1,zero,a5
;; and a3,a0,a1
;; not a5,a1
;; and a1,a4,a5
;; or a3,a3,a1
;; lbu a0,0(a3)
;; srli a3,a2,32
;; ld a2,[const(1)]
;; add a2,a3,a2
;; trap_if heap_oob##(a2 ult a3)
;; ld a4,8(a1)
;; ugt a4,a2,a4##ty=i64
;; ld a5,0(a1)
;; add a3,a5,a3
;; ld a5,[const(0)]
;; add a3,a3,a5
;; li a5,0
;; sltu a4,zero,a4
;; sub a0,zero,a4
;; and a2,a5,a0
;; not a4,a0
;; and a0,a3,a4
;; or a2,a2,a0
;; lbu a0,0(a2)
;; j label1
;; block1:
;; ret
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