Rename opcode: PMULLQ to VPMULLQ

bytecodealliance · Jun 3, 2020 · 5db384c · 5db384c
1 parent ce78ee3
commit 5db384c
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/cranelift/codegen/meta/src/isa/x86/encodings.rs b/cranelift/codegen/meta/src/isa/x86/encodings.rs
@@ -2108,7 +2108,7 @@ fn define_simd(
     {
         e.enc_32_64_maybe_isap(
             x86_pmullq,
-            rec_evex_reg_vvvv_rm_128.opcodes(&PMULLQ).w(),
+            rec_evex_reg_vvvv_rm_128.opcodes(&VPMULLQ).w(),
             Some(use_avx512dq_simd), // TODO need an OR predicate to join with AVX512VL
         );
     }

diff --git a/cranelift/codegen/meta/src/isa/x86/opcodes.rs b/cranelift/codegen/meta/src/isa/x86/opcodes.rs
@@ -471,7 +471,7 @@ pub static PMULLD: [u8; 4] = [0x66, 0x0f, 0x38, 0x40];
 
 /// Multiply the packed quadword signed integers in xmm2 and xmm3/m128 and store the low 64
 /// bits of each product in xmm1 (AVX512VL/DQ). Requires an EVEX encoding.
-pub static PMULLQ: [u8; 4] = [0x66, 0x0f, 0x38, 0x40];
+pub static VPMULLQ: [u8; 4] = [0x66, 0x0f, 0x38, 0x40];
 
 /// Multiply packed unsigned doubleword integers in xmm1 by packed unsigned doubleword integers
 /// in xmm2/m128, and store the quadword results in xmm1 (SSE2).