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Fix the ordering of reuse constraints
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elliottt committed Nov 19, 2022
1 parent 74adead commit b6aa575
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Showing 5 changed files with 47 additions and 48 deletions.
42 changes: 21 additions & 21 deletions cranelift/codegen/src/isa/s390x/inst/emit.rs
Original file line number Diff line number Diff line change
Expand Up @@ -1512,8 +1512,8 @@ impl Inst {
}
}
&Inst::AluRR { alu_op, rd, ri, rm } => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
let rd = allocs.next_writable(rd);
debug_assert_eq!(rd.to_reg(), ri);
let rm = allocs.next(rm);

Expand Down Expand Up @@ -1553,8 +1553,8 @@ impl Inst {
ri,
ref mem,
} => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
let rd = allocs.next_writable(rd);
debug_assert_eq!(rd.to_reg(), ri);
let mem = mem.with_allocs(allocs);

Expand Down Expand Up @@ -1599,8 +1599,8 @@ impl Inst {
ri,
imm,
} => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
let rd = allocs.next_writable(rd);
debug_assert_eq!(rd.to_reg(), ri);

let opcode = match alu_op {
Expand All @@ -1618,8 +1618,8 @@ impl Inst {
ri,
imm,
} => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
let rd = allocs.next_writable(rd);
debug_assert_eq!(rd.to_reg(), ri);

let opcode = match alu_op {
Expand All @@ -1637,8 +1637,8 @@ impl Inst {
ri,
imm,
} => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
let rd = allocs.next_writable(rd);
debug_assert_eq!(rd.to_reg(), ri);

let opcode = match alu_op {
Expand All @@ -1656,8 +1656,8 @@ impl Inst {
ri,
imm,
} => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
let rd = allocs.next_writable(rd);
debug_assert_eq!(rd.to_reg(), ri);

let opcode = match (alu_op, imm.shift) {
Expand All @@ -1683,8 +1683,8 @@ impl Inst {
ri,
imm,
} => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
let rd = allocs.next_writable(rd);
debug_assert_eq!(rd.to_reg(), ri);

let opcode = match (alu_op, imm.shift) {
Expand Down Expand Up @@ -1821,8 +1821,8 @@ impl Inst {
end_bit,
rotate_amt,
} => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
let rd = allocs.next_writable(rd);
debug_assert_eq!(rd.to_reg(), ri);
let rn = allocs.next(rn);

Expand Down Expand Up @@ -2165,8 +2165,8 @@ impl Inst {
rn,
ref mem,
} => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
let rd = allocs.next_writable(rd);
debug_assert_eq!(rd.to_reg(), ri);
let rn = allocs.next(rn);
let mem = mem.with_allocs(allocs);
Expand Down Expand Up @@ -2378,26 +2378,26 @@ impl Inst {
put(sink, &enc_ril_a(opcode, rd.to_reg(), imm as u32));
}
&Inst::CMov32 { rd, cond, ri, rm } => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
let rd = allocs.next_writable(rd);
debug_assert_eq!(rd.to_reg(), ri);
let rm = allocs.next(rm);

let opcode = 0xb9f2; // LOCR
put(sink, &enc_rrf_cde(opcode, rd.to_reg(), rm, cond.bits(), 0));
}
&Inst::CMov64 { rd, cond, ri, rm } => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
let rd = allocs.next_writable(rd);
debug_assert_eq!(rd.to_reg(), ri);
let rm = allocs.next(rm);

let opcode = 0xb9e2; // LOCGR
put(sink, &enc_rrf_cde(opcode, rd.to_reg(), rm, cond.bits(), 0));
}
&Inst::CMov32SImm16 { rd, cond, ri, imm } => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
let rd = allocs.next_writable(rd);
debug_assert_eq!(rd.to_reg(), ri);

let opcode = 0xec42; // LOCHI
Expand All @@ -2407,8 +2407,8 @@ impl Inst {
);
}
&Inst::CMov64SImm16 { rd, cond, ri, imm } => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
let rd = allocs.next_writable(rd);
debug_assert_eq!(rd.to_reg(), ri);

let opcode = 0xec46; // LOCGHI
Expand Down Expand Up @@ -2440,8 +2440,8 @@ impl Inst {
put(sink, &enc_ril_a(opcode, rd.to_reg(), imm.bits));
}
&Inst::Insert64UImm16Shifted { rd, ri, imm } => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
let rd = allocs.next_writable(rd);
debug_assert_eq!(rd.to_reg(), ri);

let opcode = match imm.shift {
Expand All @@ -2454,8 +2454,8 @@ impl Inst {
put(sink, &enc_ri_a(opcode, rd.to_reg(), imm.bits));
}
&Inst::Insert64UImm32Shifted { rd, ri, imm } => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
let rd = allocs.next_writable(rd);
debug_assert_eq!(rd.to_reg(), ri);

let opcode = match imm.shift {
Expand All @@ -2472,8 +2472,8 @@ impl Inst {
}

&Inst::InsertAR { rd, ri, ar } => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
let rd = allocs.next_writable(rd);
debug_assert_eq!(rd.to_reg(), ri);

let opcode = 0xb24f; // EAR
Expand Down Expand Up @@ -2526,8 +2526,8 @@ impl Inst {
}
}
&Inst::FpuCMov32 { rd, cond, ri, rm } => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
let rd = allocs.next_writable(rd);
debug_assert_eq!(rd.to_reg(), ri);
let rm = allocs.next(rm);

Expand Down Expand Up @@ -3133,8 +3133,8 @@ impl Inst {
put(sink, &enc_vrr_a(opcode, rd.to_reg(), rn, 0, 0, 0));
}
&Inst::VecCMov { rd, cond, ri, rm } => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
let rd = allocs.next_writable(rd);
debug_assert_eq!(rd.to_reg(), ri);
let rm = allocs.next(rm);

Expand Down Expand Up @@ -3235,8 +3235,8 @@ impl Inst {
ref mem,
lane_imm,
} => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
let rd = allocs.next_writable(rd);
debug_assert_eq!(rd.to_reg(), ri);
let mem = mem.with_allocs(allocs);

Expand Down Expand Up @@ -3358,8 +3358,8 @@ impl Inst {
lane_imm,
lane_reg,
} => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
let rd = allocs.next_writable(rd);
debug_assert_eq!(rd.to_reg(), ri);
let rn = allocs.next(rn);
let lane_reg = allocs.next(lane_reg);
Expand Down Expand Up @@ -3441,8 +3441,8 @@ impl Inst {
imm,
lane_imm,
} => {
let rd = allocs.next_writable(rd);
let ri = allocs.next(ri);
let rd = allocs.next_writable(rd);
debug_assert_eq!(rd.to_reg(), ri);

let opcode = match size {
Expand Down
42 changes: 21 additions & 21 deletions cranelift/codegen/src/isa/s390x/inst/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -508,36 +508,36 @@ fn s390x_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandC
collector.reg_use(rn);
}
&Inst::AluRR { rd, ri, rm, .. } => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
collector.reg_reuse_def(rd, 0);
collector.reg_use(rm);
}
&Inst::AluRX {
rd, ri, ref mem, ..
} => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
collector.reg_reuse_def(rd, 0);
memarg_operands(mem, collector);
}
&Inst::AluRSImm16 { rd, ri, .. } => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
collector.reg_reuse_def(rd, 0);
}
&Inst::AluRSImm32 { rd, ri, .. } => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
collector.reg_reuse_def(rd, 0);
}
&Inst::AluRUImm32 { rd, ri, .. } => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
collector.reg_reuse_def(rd, 0);
}
&Inst::AluRUImm16Shifted { rd, ri, .. } => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
collector.reg_reuse_def(rd, 0);
}
&Inst::AluRUImm32Shifted { rd, ri, .. } => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
collector.reg_reuse_def(rd, 0);
}
&Inst::SMulWide { rd, rn, rm } => {
collector.reg_use(rn);
Expand Down Expand Up @@ -581,8 +581,8 @@ fn s390x_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandC
}
}
&Inst::RxSBG { rd, ri, rn, .. } => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
collector.reg_reuse_def(rd, 0);
collector.reg_use(rn);
}
&Inst::RxSBGTest { rd, rn, .. } => {
Expand Down Expand Up @@ -641,8 +641,8 @@ fn s390x_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandC
ref mem,
..
} => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
collector.reg_reuse_def(rd, 0);
collector.reg_use(rn);
memarg_operands(mem, collector);
}
Expand Down Expand Up @@ -729,33 +729,33 @@ fn s390x_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandC
collector.reg_def(rd);
}
&Inst::CMov32 { rd, ri, rm, .. } | &Inst::CMov64 { rd, ri, rm, .. } => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
collector.reg_reuse_def(rd, 0);
collector.reg_use(rm);
}
&Inst::CMov32SImm16 { rd, ri, .. } | &Inst::CMov64SImm16 { rd, ri, .. } => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
collector.reg_reuse_def(rd, 0);
}
&Inst::Insert64UImm16Shifted { rd, ri, .. }
| &Inst::Insert64UImm32Shifted { rd, ri, .. } => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
collector.reg_reuse_def(rd, 0);
}
&Inst::LoadAR { rd, .. } => {
collector.reg_def(rd);
}
&Inst::InsertAR { rd, ri, .. } => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
collector.reg_reuse_def(rd, 0);
}
&Inst::FpuMove32 { rd, rn } | &Inst::FpuMove64 { rd, rn } => {
collector.reg_def(rd);
collector.reg_use(rn);
}
&Inst::FpuCMov32 { rd, ri, rm, .. } | &Inst::FpuCMov64 { rd, ri, rm, .. } => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
collector.reg_reuse_def(rd, 0);
collector.reg_use(rm);
}
&Inst::FpuRR { rd, rn, .. } => {
Expand Down Expand Up @@ -912,8 +912,8 @@ fn s390x_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandC
collector.reg_use(rn);
}
&Inst::VecCMov { rd, ri, rm, .. } => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
collector.reg_reuse_def(rd, 0);
collector.reg_use(rm);
}
&Inst::MovToVec128 { rd, rn, rm } => {
Expand All @@ -937,8 +937,8 @@ fn s390x_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandC
&Inst::VecLoadLane {
rd, ri, ref mem, ..
} => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
collector.reg_reuse_def(rd, 0);
memarg_operands(mem, collector);
}
&Inst::VecLoadLaneUndef { rd, ref mem, .. } => {
Expand All @@ -960,8 +960,8 @@ fn s390x_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandC
&Inst::VecLoadLaneRev {
rd, ri, ref mem, ..
} => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
collector.reg_reuse_def(rd, 0);
memarg_operands(mem, collector);
}
&Inst::VecInsertLane {
Expand All @@ -971,8 +971,8 @@ fn s390x_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandC
lane_reg,
..
} => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
collector.reg_reuse_def(rd, 0);
collector.reg_use(rn);
if lane_reg != zero_reg() {
collector.reg_use(lane_reg);
Expand All @@ -997,8 +997,8 @@ fn s390x_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandC
}
}
&Inst::VecInsertLaneImm { rd, ri, .. } => {
collector.reg_reuse_def(rd, 1);
collector.reg_use(ri);
collector.reg_reuse_def(rd, 0);
}
&Inst::VecReplicateLane { rd, rn, .. } => {
collector.reg_def(rd);
Expand Down Expand Up @@ -2184,8 +2184,8 @@ impl Inst {
ri,
ref imm,
} => {
let rd = pretty_print_reg_mod(rd, ri, allocs);
let cond = cond.pretty_print_default();
let rd = pretty_print_reg_mod(rd, ri, allocs);
format!("lochi{} {}, {}", cond, rd, imm)
}
&Inst::CMov64SImm16 {
Expand Down Expand Up @@ -2217,8 +2217,8 @@ impl Inst {
}
}
&Inst::FpuCMov32 { rd, cond, ri, rm } => {
let (rd, rd_fpr) = pretty_print_fpr(rd.to_reg(), allocs);
let _ri = allocs.next(ri);
let (rd, rd_fpr) = pretty_print_fpr(rd.to_reg(), allocs);
let (rm, rm_fpr) = pretty_print_fpr(rm, allocs);
if rd_fpr.is_some() && rm_fpr.is_some() {
let cond = cond.invert().pretty_print_default();
Expand Down
2 changes: 1 addition & 1 deletion cranelift/codegen/src/isa/s390x/inst/regs.rs
Original file line number Diff line number Diff line change
Expand Up @@ -202,8 +202,8 @@ pub fn pretty_print_reg_mod(
ri: Reg,
allocs: &mut AllocationConsumer<'_>,
) -> String {
let output = allocs.next_writable(rd).to_reg();
let input = allocs.next(ri);
let output = allocs.next_writable(rd).to_reg();
if output == input {
show_reg(output)
} else {
Expand Down
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