Implements convert low signed integer to float for x64 simd #2771
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Also .. this patch is tested against the spec tests for "f64x2.convert_low_i32x4_s" |
| Convert signed integer to floating point. | ||
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| Each lane in `x` is interpreted as a signed integer and converted to | ||
| floating point. |
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I think we should add something about rounding like in fcvt_from_sint and something describing what the low part of the name means.
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I mean, it's not like the SIMD documentation is much more verbose... perhaps that should get fixed too. I think we need to say something about how the two lowest i32s in the vector (lanes 0 and 1) are the ones converted to the f64. From the Intel reference:
CVTDQ2PD (128-bit Legacy SSE version)
DEST[63:0] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[MAXVL-1:128] (unmodified)
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Yes, this is a good point. In updating the comments I just used language of half. That is because the "fcvt_low_from_sint" can also support AVX-512 where we could convert the "four" lowest i32s. That instruction doesn't exist of course in the spec, but could be a candidate for a future iteration of the spec or relaxed simd.
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