Split Fmla and Bsl out into new VecRRRMod op
#4638
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Separates the following opcodes for AArch64 into a separate `VecALUModOp` enum, which is emitted via the `VecRRRMod` instruction. This separates vector ALU instructions which modify a register from instructions which write to a new register: - `Bsl` - `Fmla` Addresses [a discussion](bytecodealliance#4608 (comment)) in bytecodealliance#4608. Copyright (c) 2022 Arm Limited
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Separates the following opcodes for AArch64 into a separate
VecALUModOpenum,which is emitted via the
VecRRRModinstruction. This separates vector ALUinstructions which modify a register from instructions which write to a new register:
BslFmlaAddresses a discussion in #4608.
Copyright (c) 2022 Arm Limited