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riscv64: Implement SIMD bitwise operations #6419

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merged 8 commits into from
May 22, 2023

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afonso360
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👋 Hey,

This PR implements the remaining bitwise operations so that we pass simd_bitwise.wast, it also adds the .vx and .vi versions of the pre-existing bitwise operations (band, bor, bxor).

@afonso360 afonso360 requested review from a team as code owners May 20, 2023 19:10
@afonso360 afonso360 requested review from fitzgen and removed request for a team May 20, 2023 19:10
@github-actions github-actions bot added cranelift Issues related to the Cranelift code generator isle Related to the ISLE domain-specific language labels May 20, 2023
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Looks great, thanks! Additionally thanks for all the new runtests!

@afonso360 afonso360 added this pull request to the merge queue May 22, 2023
Merged via the queue into bytecodealliance:main with commit 2bbae47 May 22, 2023
@afonso360 afonso360 deleted the riscv-simd-bitwise branch May 22, 2023 18:16
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