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riscv64: Implement SIMD popcnt #6587

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merged 2 commits into from
Jun 17, 2023

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afonso360
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@afonso360 afonso360 commented Jun 16, 2023

👋 Hey,

This PR Implements the SIMD popcnt instruction for RISC-V. We don't have a native version of this, so we need to use one of the popular algorithms that normally replaces the native instruction. This is the variant that LLVM uses for element types larger than i8, they also have a shorter implementation for i8x16, but I didn't implement it here.

I also checked what V8 produces and they do a loop that sums each bit. In our case that would involve having a custom instruction and I didn't really want to do that.

@afonso360 afonso360 added the cranelift:area:riscv64 Issues related to the RISC-V 64 backend. label Jun 16, 2023
@afonso360 afonso360 requested a review from a team as a code owner June 16, 2023 12:19
@afonso360 afonso360 requested review from cfallin and removed request for a team June 16, 2023 12:19
@github-actions github-actions bot added the cranelift Issues related to the Cranelift code generator label Jun 16, 2023
@jameysharp
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Maybe @itsrainy would like to review this, after writing essentially the same lowering for Winch/x86 this week in #6531?

@cfallin
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cfallin commented Jun 16, 2023

I'm happy to review if not but please feel free!

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this looks good to me!

@afonso360 afonso360 added this pull request to the merge queue Jun 17, 2023
Merged via the queue into bytecodealliance:main with commit 7718102 Jun 17, 2023
@afonso360 afonso360 deleted the riscv-simd-popcnt branch June 17, 2023 09:52
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4 participants