riscv64: Implement SIMD floating point conversion instructions #6924
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
afonso360
added
the
cranelift:area:riscv64
github-actions
bot
added
cranelift
Subscribe to Label Action
This issue or pull request has been labeled: "cranelift", "cranelift:area:riscv64", "isle"
Thus the following users have been cc'd because of the following labels:
To subscribe or unsubscribe from this label, edit the |
afonso360
force-pushed
the
riscv-simd-ftoi
branch
from
5e473f2 to
e99d8ec
Compare
alexcrichton
approved these changes
Aug 30, 2023
eduardomourar
pushed a commit
to eduardomourar/wasmtime
that referenced
this pull request
Sep 6, 2023
…odealliance#6924) * riscv64: Implement SIMD `fvpromote_low`/`fvdemote` * riscv64: Implement SIMD `fcvt_from_{u,s}int` * riscv64: Implement SIMD `fcvt_to_{u,s}int_sat` * riscv64: Use `i8_to_imm5` constructor
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
👋 Hey,
This PR implements the floating point conversion instructions (
fvdemote,fvpromote_low,fcvt_{to,from}_{u,s}int{,_sat}) on the RISC-V backend.Almost all instructions match 1-to-1 with the WASM spec, except
fcvt_to_{u,s}int_sat, where NaN's need to be manually zeroed out. And onfvdemoteRISC-V leaves the upper lanes undefined, so we also zero them out manually.🎉 With this PR we now have SIMD fully implemented for RISC-V🎉
There is 1 test that is not passing yet, but I think that is due to a NaN payload bit mismatch that is allowed by the spec. But I'm going to open a separate issue to confirm that.
(This PR is built on top of #6920 so we need to merge that one first)