riscv64: Add remaining Zfa Instructions #8582
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afonso360
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cfallin
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May 8, 2024
| ; fsd fs10, 0x10(sp) | ||
| ; fsd fs11, 8(sp) | ||
| ; block1: ; offset 0x40 | ||
| ; .byte 0x53, 0x05, 0x10, 0xf0 |
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interesting that Capstone doesn't yet support these flis; does a newer version exist that does?
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Capstone in general doesn't support any RISC-V extension, last time I checked the RISC-V support seemed a bit abandoned, but I'll go check again.
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I had a look at the release notes for the capstone engine for the past year or so. There aren't many RISC-V specific fixes, and none of them add any extensions 😞
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👋 Hey,
This PR adds support for the remaining instructions in the Zfa extension (introduced in #8536).
The first one is
fround.{s,d}that is a direct match of all of our float rounding instructions (ceil,floor,trunc,nearest) depending on how the instruction is encoded.The second one is
fli.{s,d}that loads a floating point constant from a predefined table of constants. Additionally I've also added a rule that supports loading the negated constant and then subsequently inverting the sign bit withfneg.There are additional instructions in Zfa, but none that can be easily matched with our IR.