Merge pull request #517 from byuccl/koios

koios adjustments

bfasst/flows/flow.py

@@ -3,6 +3,7 @@
 import abc
 
 from bfasst import config
+from bfasst.yaml_parser import DesignParser
 from bfasst.paths import BUILD_PATH, DESIGNS_PATH
 
 
@@ -62,6 +63,9 @@ def __init__(self, design_path):
         super().__init__()
         self.design_path = design_path
         self.design_build_path = BUILD_PATH / design_path.relative_to(DESIGNS_PATH)
+        design_yaml = self.design_path / "design.yaml"
+        parser = DesignParser(design_yaml)
+        self.part = parser.part
 
 
 class FlowNoDesign(FlowBase):

bfasst/tools/rev_bit/xray.py

@@ -1,7 +1,7 @@
 """Tool to create rule and build snippets that reverse a bitstream using xray."""
 
 import chevron
-from bfasst import config
+from bfasst.utils.general import get_family_from_part
 from bfasst.paths import (
     NINJA_BUILD_PATH,
     REV_BIT_TOOLS_PATH,
@@ -45,7 +45,7 @@ def create_build_snippets(self):
                     "fasm2bels_path": FASM2BELS_PATH,
                     "fasm2bels_python_path": FASM2BELS_PYTHON_PATH,
                     "bit_to_fasm_path": XRAY_PATH / "utils" / "bit2fasm.py",
-                    "db_root": XRAY_DB_PATH / config.PART_FAMILY,
+                    "db_root": XRAY_DB_PATH / get_family_from_part(self.flow.part),
                     "part": self.flow.part,
                     "input_xdc": self.xdc_input,
                 },

bfasst/utils/general.py

@@ -223,3 +223,12 @@ def json_write_if_changed(path, json_str):
     if not json_equivalent:
         with open(path, "w") as f:
             f.write(json_str)
+
+
+def get_family_from_part(part):
+    """
+    part (string): e.g., "xc7a200tsbg484-1"
+    Returns the part family name based on the part name,
+    will have to be changed if we start supporting more part families
+    """
+    return "kintex7" if part[3] == "k" else "artix7"

bfasst/yaml_parser.py

@@ -103,6 +103,9 @@ def __init__(self, yaml_path=None):
 
         props = YamlParser(yaml_path).props
         self.top = props["top"]
+        if "part" in props:
+            self.part = props["part"]
+
         if "vhdl_libs" in props:
             self.vhdl_libs = props["vhdl_libs"]
 

designs/koios/bwave_like.float.large/bwave_large_random.sv

@@ -278,14 +278,19 @@ Randomize input to bwave_large
 module bwave_large_random (
     input logic clk,
     input logic rst,
-    output logic [`DRAM_DWIDTH-1:0] output_data_DRAM,
+    // get rid of the vector output and output a single bit instead
+    output logic single_xor_out,
+    // output logic [`DRAM_DWIDTH-1:0] output_data_DRAM,
     output logic [`DRAM_AWIDTH-1:0] dram_addr,
     output logic dram_write_enable,
     output logic get_instr,
     output logic [`INSTR_MEM_AWIDTH-1:0] get_instr_addr
 );
 
 logic [`DRAM_DWIDTH-1:0] input_data_DRAM;
+// add in a temp vector for output data that we can xor into the single bit output
+logic [`DRAM_DWIDTH-1:0] internal_output_data_DRAM;
+
 RandomNumberGenerator #(`DRAM_DWIDTH, 0) rng (
     .clk(clk),
     .reset(rst),
@@ -303,13 +308,15 @@ NPU npu0(
     rst,
     instruction,
     input_data_DRAM,
-    output_data_DRAM,
+    internal_output_data_DRAM,
     dram_addr,
     dram_write_enable,
     get_instr,
     get_instr_addr,
     clk
 );
 
+assign single_xor_out = ^internal_output_data_DRAM;
+
 endmodule
 

designs/koios/bwave_like.float.large/design.yaml

@@ -1 +1,3 @@
 top: bwave_large_random
+
+part: xc7k410tfbg900-1

designs/koios/dnnweaver/design.yaml

@@ -1 +1,3 @@
 top: cl_wrapper_random
+
+part: xc7k410tfbg900-1

designs/koios/gemm_layer/design.yaml

@@ -1 +1,3 @@
 top: gemm_random
+
+part: xc7k410tfbg900-1