Added sort all flag to the Verilog composer

[ganeshgore]

In some cases, the composed netlist is maintained in version controlled system. which expects the deterministic output during every run. Setting sort_all flag to true, sort each element in the Verilog netlist (like input/output declaration, instance declaration, and ports, declarations).

[jacobdbrown4]

This is a good option. And thanks for setting the pull request to go to the next_release branch. We have other changes that have been pushed to the next release branch that conflict with this though. Can you maybe update your side to match our next_release branch and then we can merge it in?

[jacobdbrown4]

@ganeshgore thanks for adding this feature. Can you resolve the conflicts? And then I'll accept the pull request.

[jacobdbrown4]

@ganeshgore I merged your other pull request but now that caused this one to have conflicts. You may have to update your composer_sort_all branch now.