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calint · May 26, 2024 · 5e0e9c0 · 5e0e9c0
1 parent 3790ef3
commit 5e0e9c0
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Showing 2 changed files with 5 additions and 3 deletions.
diff --git a/riscv.srcs/sources_1/new/SoC.v b/riscv.srcs/sources_1/new/SoC.v
@@ -32,8 +32,8 @@ wire [6:0] funct7 = ir[31:25];
 wire signed [31:0] I_imm12 = {{20{ir[31]}}, ir[31:20]};
 wire [31:0] U_imm20 = {ir[31:12], {12{1'b0}}};
 wire signed [31:0] S_imm12 = {{20{ir[31]}}, ir[31:25], ir[11:7]};
-wire signed [31:0] B_imm12 = {{20{ir[31]}}, ir[31], ir[7], ir[30:25], ir[11:8], 1'b0};
-wire signed [31:0] J_imm20 = {{20{ir[31]}}, ir[31], ir[19:12], ir[20], ir[30:21], 1'b0};
+wire signed [31:0] B_imm12 = {{20{ir[31]}}, ir[7], ir[30:25], ir[11:8], 1'b0};
+wire signed [31:0] J_imm20 = {{12{ir[31]}}, ir[19:12], ir[20], ir[30:21], 1'b0};
 
 reg [31:0] regs_rd_wd; // data for write to register 'rd' if 'regs_rd_we' is enabled
 reg regs_rd_we;
@@ -65,6 +65,8 @@ always @* begin
     ram_reA = 0;
     is_ld = 0;
     bubble = 0;
+    rs1_dat = 0;
+    rs2_dat = 0;
     pc_nxt = pc + 4;
 
     if (!is_bubble) begin

diff --git a/riscv.xpr b/riscv.xpr
@@ -60,7 +60,7 @@
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="cmod-s7-25"/>
     <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
-    <Option Name="WTXSimLaunchSim" Val="623"/>
+    <Option Name="WTXSimLaunchSim" Val="624"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>