Fix compiler warnings

capstone-engine · Sep 12, 2023 · 2d8dad6 · 2d8dad6
1 parent f4ea7e1
commit 2d8dad6
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Showing 6 changed files with 25 additions and 14 deletions.
diff --git a/MCInst.c b/MCInst.c
@@ -279,9 +279,9 @@ uint64_t MCInst_getOpVal(MCInst *MI, unsigned OpNum)
 		return MCOperand_getReg(op);
 	else if (MCOperand_isImm(op))
 		return MCOperand_getImm(op);
-	else
-		assert(0 && "Operand type not handled in this getter.");
-		return false;
+
+	assert(0 && "Operand type not handled in this getter.");
+	return false;
 }
 
 void MCInst_setIsAlias(MCInst *MI, bool Flag) {

diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c
@@ -377,8 +377,10 @@ void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O)
 {
 	MCOperand *Op = MCInst_getOperand(MI, (OpNum));
 	if (!MCOperand_isImm(Op) || MI->csh->PrintBranchImmNotAsAddress ||
-	    getUseMarkup())
-		return printOperand(MI, OpNum, O);
+	    getUseMarkup()) {
+		printOperand(MI, OpNum, O);
+		return;
+	}
 	int64_t Imm = MCOperand_getImm(Op);
 	// For ARM instructions the PC offset is 8 bytes, for Thumb instructions it
 	// is 4 bytes.
@@ -1556,8 +1558,10 @@ void printModImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
 	MCOperand *Op = MCInst_getOperand(MI, (OpNum));
 
 	// Support for fixups (MCFixup)
-	if (MCOperand_isExpr(Op))
-		return printOperand(MI, OpNum, O);
+	if (MCOperand_isExpr(Op)) {
+		printOperand(MI, OpNum, O);
+		return;
+	}
 
 	unsigned Bits = MCOperand_getImm(Op) & 0xFF;
 	unsigned Rot = (MCOperand_getImm(Op) & 0xF00) >> 7;

diff --git a/arch/PowerPC/PPCGenDisassemblerTables.inc b/arch/PowerPC/PPCGenDisassemblerTables.inc
@@ -9819,7 +9819,7 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
       NumToSkip |= (*Ptr++) << 16; \
       /* Perform the decode operation. */ \
       MCInst_setOpcode(MI, Opc); \
-      bool DecodeComplete; \
+      bool DecodeComplete = false; \
       S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \
       if (DecodeComplete) { \
         /* Decoding complete. */ \

diff --git a/arch/PowerPC/PPCInstPrinter.c b/arch/PowerPC/PPCInstPrinter.c
@@ -503,8 +503,10 @@ void printU16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
 void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo, SStream *O)
 {
 	add_cs_detail(MI, PPC_OP_GROUP_BranchOperand, OpNo);
-	if (!MCOperand_isImm(MCInst_getOperand(MI, (OpNo))))
-		return printOperand(MI, OpNo, O);
+	if (!MCOperand_isImm(MCInst_getOperand(MI, (OpNo)))) {
+		printOperand(MI, OpNo, O);
+		return;
+	}
 	int32_t Imm = SignExtend32(
 		((unsigned)MCOperand_getImm(MCInst_getOperand(MI, (OpNo)))
 		 << 2),
@@ -532,8 +534,10 @@ void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo, SStream *O)
 void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O)
 {
 	add_cs_detail(MI, PPC_OP_GROUP_AbsBranchOperand, OpNo);
-	if (!MCOperand_isImm(MCInst_getOperand(MI, (OpNo))))
-		return printOperand(MI, OpNo, O);
+	if (!MCOperand_isImm(MCInst_getOperand(MI, (OpNo)))) {
+		printOperand(MI, OpNo, O);
+		return;
+	}
 
 	printInt32(O, SignExtend32(((unsigned)MCOperand_getImm(
 					    MCInst_getOperand(MI, (OpNo)))

diff --git a/cstool/cstool_powerpc.c b/cstool/cstool_powerpc.c
@@ -124,7 +124,7 @@ void print_insn_detail_ppc(csh handle, cs_insn *ins)
 		}
 		if (ppc->bc.pred_ctr != PPC_PRED_INVALID)
 			printf("\t\tpred CTR: %s\n", get_pred_name(ppc->bc.pred_ctr));
-		if (ppc->bc.hint != PPC_BH_INVALID)
+		if (ppc->bc.hint != PPC_BR_NOT_GIVEN)
 			printf("\t\thint: %u\n", ppc->bc.hint);
 	}
 

diff --git a/include/capstone/arm.h b/include/capstone/arm.h
@@ -148,14 +148,17 @@ typedef enum PredBlockMask {
 inline static const char *ARMVPTPredToString(ARMVCC_VPTCodes CC)
 {
   switch (CC) {
+  default:
+    assert(0 && "Unknown VPT code");
+    break;
   case ARMVCC_None:
     return "none";
   case ARMVCC_Then:
     return "t";
   case ARMVCC_Else:
     return "e";
   }
-  assert(0 && "Unknown VPT code");
+  return NULL;
 }
 
 inline static unsigned ARMVectorCondCodeFromString(const char CC)